Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators

📝 Original Info

• Title: Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators
• ArXiv ID: 2512.15251
• Date: 2025-12-17
• Authors: Michael Mecik, Martin Kumm

📝 Abstract

Fully parallel neural network accelerators on fieldprogrammable gate arrays (FPGAs) offer high throughput for latency-critical applications but face hardware resource constraints. Weightless neural networks (WNNs) efficiently replace arithmetic with logic-based inference. Differential weightless neural networks (DWN) further optimize resource usage by learning connections between encoders and LUT layers via gradient-based training. However, DWNs rely on thermometer encoding, and the associated hardware cost has not been fully evaluated. We present a DWN hardware generator that includes thermometer encoding explicitly. Experiments on the Jet Substructure Classification (JSC) task show that encoding can increase LUT usage by up to 3.20×, dominating costs in small networks and highlighting the need for encoding-aware hardware design in DWN accelerators.

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