On-chip Few-shot Learning with Surrogate Gradient Descent on a Neuromorphic Processor

[AC]Arrenhius & Current [AER]Address Event Representation [AEX]AER EXtension board [AMDA]“AER Motherboard with D/A converters” [API]Application Programming Interface [BM]Boltzmann Machine [CAVIAR]Convolution AER Vision Architecture for Real-Time [CCN]Cooperative and Competitive Network [CD]Contrastive Divergence [CMOS]Complementary Metal–Oxide–Semiconductor [COTS]Commercial Off-The-Shelf [CPU]Central Processing Unit [CV]Coefficient of Variation [CV]Coefficient of Variation [DAC]Digital–to–Analog [DBN]Deep Belief Network [DFA]Deterministic Finite Automaton [DFA]Deterministic Finite Automaton [DIVMOD3]divisibility of a number by 3 [DPE]Dynamic Parameter Estimation [DPI]Differential-Pair Integrator [DSP]Digital Signal Processor [DVS]Dynamic Vision Sensor [EDVAC]Electronic Discrete Variable Automatic Computer [EI&F]Exponential Integrate & Fire [EIN]Excitatory–Inhibitory Network [EPSC]Excitatory Post-Synaptic Current [eRBP]event-driven Random Back-Propagation [EPSP]Excitatory Post–Synaptic Potential [FPGA]Field Programmable Gate Array [FSM]Finite State Machine [GPU]Graphical Processing Unit [HAL]Hardware Abstraction Layer [H&H]Hodgkin & Huxley [HMM]Hidden Markov Model [HW]Hardware [hWTA]Hard Winner–Take–All [IF2DWTA]Integrate & Fire 2–Dimensional WTA [I&F]Integrate & Fire [IFSLWTA]Integrate & Fire Stop Learning WTA [INCF]International Neuroinformatics Coordinating Facility [INI]Institute of Neuroinformatics [IO]Input-Output [IPSC]Inhibitory Post-Synaptic Current [ISI]Inter–Spike Interval [JFLAP]Java - Formal Languages and Automata Package [LI&F]Leaky Integrate & Fire [LSM]Liquid State Machine [LTD]Long-Term Depression [LTI]Linear Time-Invariant [LTP]Long-Term Potentiation [LTU]Linear Threshold Unit [MSE]Mean-Squared Error [NHML]Neuromorphic Hardware Mark-up Language [NMDA]NMDA [NE]Neuromorphic Engineering [PCB]Printed Circuit Board [PRC]Phase Response Curve [PSC]Post-Synaptic Current [PSP]Post–Synaptic Potential [KL]Kullback-Leibler [RNN]Recurrent Neural Network [RRAM]Resistive Random-Access Memory [RBM]Restricted Boltzmann Machine [ROC]Receiver Operator Characteristic [SAC]Selective Attention Chip [SCD]Spike-Based Contrastive Divergence [SCX]Silicon CorteX [SSM]Synaptic Sampling Machines [SNN]Spiking Neural Network [STDP]Spike Time Dependent Plasticity [SW]Software [SWTA]Soft Winner–Take–All [VHDL]VHSIC Hardware Description Language [VLSI]Very Large Scale Integration [WTA]Winner–Take–All [XML]eXtensible Mark-up Language