Few-Shot Learning with Surrogate Gradient Descent on a Neuromorphic Processor

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📝 Original Paper Info

- Title: On-chip Few-shot Learning with Surrogate Gradient Descent on a Neuromorphic Processor
- ArXiv ID: 1910.04972
- Date: 2019-11-06
- Authors: Kenneth Stewart, Garrick Orchard, Sumit Bam Shrestha, Emre Neftci

📝 Abstract

Recent work suggests that synaptic plasticity dynamics in biological models of neurons and neuromorphic hardware are compatible with gradient-based learning (Neftci et al., 2019). Gradient-based learning requires iterating several times over a dataset, which is both time-consuming and constrains the training samples to be independently and identically distributed. This is incompatible with learning systems that do not have boundaries between training and inference, such as in neuromorphic hardware. One approach to overcome these constraints is transfer learning, where a portion of the network is pre-trained and mapped into hardware and the remaining portion is trained online. Transfer learning has the advantage that pre-training can be accelerated offline if the task domain is known, and few samples of each class are sufficient for learning the target task at reasonable accuracies. Here, we demonstrate on-line surrogate gradient few-shot learning on Intel's Loihi neuromorphic research processor using features pre-trained with spike-based gradient backpropagation-through-time. Our experimental results show that the Loihi chip can learn gestures online using a small number of shots and achieve results that are comparable to the models simulated on a conventional processor.

💡 Summary & Analysis

This paper explores the integration of gradient-based learning with neuromorphic hardware to perform few-shot learning, specifically using Intel's Loihi processor. The main issue addressed is that traditional gradient-based learning methods are time-consuming and require datasets to be independently and identically distributed, which is incompatible with systems like neuromorphic hardware where there's no clear boundary between training and inference phases. To overcome this challenge, the authors use transfer learning, where a portion of the network is pre-trained offline and then mapped into hardware, while the rest continues to learn online. The key innovation lies in leveraging spike-based gradient backpropagation for feature extraction before transferring it to Loihi for further online training. Experimental results demonstrate that Loihi can achieve comparable performance to conventional processors when learning gestures with a small number of samples. This breakthrough signifies that neuromorphic hardware can support efficient and fast online learning, opening up possibilities in real-time data processing applications.

📄 Full Paper Content (ArXiv Source)

\[AC\]Arrenhius & Current \[AER\]Address Event Representation \[AEX\]AER EXtension board \[AMDA\]“AER Motherboard with D/A converters” \[API\]Application Programming Interface \[BM\]Boltzmann Machine \[CAVIAR\]Convolution AER Vision Architecture for Real-Time \[CCN\]Cooperative and Competitive Network \[CD\]Contrastive Divergence \[CMOS\]Complementary Metal–Oxide–Semiconductor \[COTS\]Commercial Off-The-Shelf \[CPU\]Central Processing Unit \[CV\]Coefficient of Variation \[CV\]Coefficient of Variation \[DAC\]Digital–to–Analog \[DBN\]Deep Belief Network \[DFA\]Deterministic Finite Automaton \[DFA\]Deterministic Finite Automaton \[DIVMOD3\]divisibility of a number by 3 \[DPE\]Dynamic Parameter Estimation \[DPI\]Differential-Pair Integrator \[DSP\]Digital Signal Processor \[DVS\]Dynamic Vision Sensor \[EDVAC\]Electronic Discrete Variable Automatic Computer \[EI&F\]Exponential Integrate & Fire \[EIN\]Excitatory–Inhibitory Network \[EPSC\]Excitatory Post-Synaptic Current \[eRBP\]event-driven Random Back-Propagation \[EPSP\]Excitatory Post–Synaptic Potential \[FPGA\]Field Programmable Gate Array \[FSM\]Finite State Machine \[GPU\]Graphical Processing Unit \[HAL\]Hardware Abstraction Layer \[H&H\]Hodgkin & Huxley \[HMM\]Hidden Markov Model \[HW\]Hardware \[hWTA\]Hard Winner–Take–All \[IF2DWTA\]Integrate & Fire 2–Dimensional WTA \[I&F\]Integrate & Fire \[IFSLWTA\]Integrate & Fire Stop Learning WTA \[INCF\]International Neuroinformatics Coordinating Facility \[INI\]Institute of Neuroinformatics \[IO\]Input-Output \[IPSC\]Inhibitory Post-Synaptic Current \[ISI\]Inter–Spike Interval \[JFLAP\]Java - Formal Languages and Automata Package \[LI&F\]Leaky Integrate & Fire \[LSM\]Liquid State Machine \[LTD\]Long-Term Depression \[LTI\]Linear Time-Invariant \[LTP\]Long-Term Potentiation \[LTU\]Linear Threshold Unit \[MSE\]Mean-Squared Error \[NHML\]Neuromorphic Hardware Mark-up Language \[NMDA\]NMDA \[NE\]Neuromorphic Engineering \[PCB\]Printed Circuit Board \[PRC\]Phase Response Curve \[PSC\]Post-Synaptic Current \[PSP\]Post–Synaptic Potential \[KL\]Kullback-Leibler \[RNN\]Recurrent Neural Network \[RRAM\]Resistive Random-Access Memory \[RBM\]Restricted Boltzmann Machine \[ROC\]Receiver Operator Characteristic \[SAC\]Selective Attention Chip \[SCD\]Spike-Based Contrastive Divergence \[SCX\]Silicon CorteX \[SSM\]Synaptic Sampling Machines \[SNN\]Spiking Neural Network \[STDP\]Spike Time Dependent Plasticity \[SW\]Software \[SWTA\]Soft Winner–Take–All \[VHDL\]VHSIC Hardware Description Language \[VLSI\]Very Large Scale Integration \[WTA\]Winner–Take–All \[XML\]eXtensible Mark-up Language

📊 논문 시각자료 (Figures)

Figure 1



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