Recent advances in photonic inverse design have demonstrated the ability to automatically synthesize compact, high-performance photonic components that surpass conventional, hand-designed structures, offering a promising path toward scalable and functionality-rich photonic hardware. However, the practical deployment of inverse-designed PICs is bottlenecked by manufacturability: their irregular, subwavelength geometries are highly sensitive to fabrication variations, leading to large performance degradation, low yield, and a persistent gap between simulated optimality and fabricated performance. Unlike electronics, photonics lacks a systematic, flexible mask optimization flow. Fabrication deviations in photonic components cause large optical response drift and compounding error in cascaded circuits, while calibrating fabrication models remains costly and expertise-heavy, often requiring repeated fabrication cycles that are inaccessible to most designers. To bridge this gap, we introduce PRISM, a photonics-informed inverse lithography workflow that makes photonic mask optimization data-efficient, reliable, and optics-informed. PRISM (i) synthesizes compact, informative calibration patterns to minimize required fabrication data, (ii) trains a physics-grounded differentiable fabrication model, enabling gradient-based optimization, and (iii) performs photonics-informed inverse mask optimization that prioritizes performance-critical features beyond geometry matching. Across multiple inverse-designed components with both electron-beam lithography and deep ultra-violet photolithography processes, PRISM significantly boosts post-fabrication performance and yield while reducing calibration area and turnaround time, enabling and democratizing manufacturable and high-yield inverse-designed photonic hardware at scale.
1 Introduction Photonic integrated circuits (PICs) are emerging as a foundational hardware platform for highbandwidth communication [1,2], optical interconnects [1][2][3][4][5], and speed-of-light computing [6][7][8][9], with growing adoption in various key use domains, e.g., artificial intelligence (AI) systems, sensing, quantum, scientific discovery, etc. Yet despite this promise, the practical design and deployment of complex PICs at scale remain constrained by a manufacturing reality: what is fabricated on wafer can deviate substantially from the intended design. For subwavelength photonic structures, e.g., gratings, inverse-designed patterns, these fine-grained structures often suffer from huge geometric deviations leading to large performance degradation and malfunction, as illustrated in Fig. 1a. This becomes especially problematic in cascaded circuits, where small component-level errors can accumulate into system-level failure. This challenge is most acute for photonic inverse design [10], which has emerged as a powerful paradigm for automatically synthesizing compact, high-performance components that surpass conventional hand-designed structures, one of the most promising pathways to achieve scalability breakthroughs in photonic hardware. By replacing brittle expert heuristics with optimization, inverse design unlocks irregular, high-degree-of-freedom photonic designs and new functionality at high packing density. However, the fine-grained features that enable superior numerical performance often make inverse-designed layouts difficult to manufacture reliably at scale [10].
In production-oriented deep ultraviolet (DUV) fabrication processes in photonic foundries, e.g., 193 nm technology node, inverse-designed patterns can, in general, be considered infeasible to manufacture due to severe distortions (e.g., rounding, blurring, bridging) that lead to near-zero yield. Electron-beam lithography (EBL) can provide higher patterning resolution for laboratory demonstrations, but it remains costly and slow for high-volume manufacturing and still exhibits non-ideal distortion. As illustrated in Fig. 1b, DUV fabrication induces substantially larger FoM degradation and a much heavier worst-case tail than EBL across representative photonic devices, underscoring the manufacturability gap for inverse-designed layouts under DUV. Figure 1c further shows that the wavelength division multiplexing transmission is jointly sensitive to lithography defocus and resist threshold, exhibiting a narrow high-performance process window. As a result, inverse-designed photonics frequently remains difficult to translate from a theoretically plausible concept into deployable, repeatable hardware, particularly when building larger circuits from many sensitive building blocks. Today, designers often cope through expensive trial-and-error: imposing conservative design rules, sacrificing geometric degrees of freedom with smoothing, running extensive parameter sweeps to search for a feasible design, and iteratively re-tapingout designs based on sparse fabrication feedback. This workflow is slow (year-long), high-cost, expertise-heavy, and fundamentally at odds with the promise of inverse design: it either sacrifices performance or fails to achieve robust yield.
A natural question is why photonics cannot simply adopt the mature design-for-manufacturing (DFM) [11] stack from electronic design automation (EDA) [12]. In electronics, foundries routinely apply optical proximity correction (OPC) [13] and inverse lithography (ILT) [14] to optimize masks and compensate for process effects. In photonics, two obstacles break this direct transfer. ➊ Photonic hardware performance relies on complicated light propagation behavior; mask correction objectives based purely on geometric similarity are not sufficient, i.e., “close geometry” does not imply “close function.” Optical response arises from nonlocal electromagnetic interactions (scattering, interference, resonance, etc) and is often dominated by a subset of sensitivity-critical features, so errors in a small region can dominate performance even when global pixel-wise error is small, illustrated in Fig. 2a. Moreover, systematic geometric biases, such as globally biased over-/under-etch, can be especially detrimental because they coherently shift effective widths, duty cycles, and phase accumulation across the device, leading to pronounced performance degradation even with a lower 𝐿 2 fabrication error, as shown in Fig. 2b. ➋ Accurate lithography modeling is expensive and process-specific: foundry details are often proprietary, and purely data-driven fabrication surrogates can require large calibration datasets. When trained with limited data, black-box neural models may produce unreliable gradients, undermining gradient-based inverse lithography optimization where stability depends on smoothness, generalization, and physically plausible sensitivities, as shown in Fig. 2c. These gaps motivate a
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