Test and verification are essential activities in hardware and system design, but their complexity grows significantly with increasing system sizes. While Behavior Driven Development (BDD) has proven effective in software engineering, it is not yet well established in hardware design, and its practical use remains limited. One contributing factor is the manual effort required to derive precise behavioral scenarios from textual specifications. Recent advances in Large Language Models (LLMs) offer new opportunities to automate this step. In this paper, we investigate the use of LLM-based techniques to support BDD in the context of hardware design.
Test and verification are central tasks in modern system design. With the continuous increase in system complexity and size, these tasks are becoming even more critical to ensure functional correctness and reliability. In the software domain, Test Driven Development (TDD) is a well-established methodology that has demonstrated several advantages in improving quality and reducing development effort [1][2][3]. As a further evolution of this idea, Behavior-Driven Development (BDD) has been introduced, offering a more structured and behavior-oriented view on specification and testing [3][4][5][6][7][8].
Recently, BDD has also gained attention in the hardware domain [9,10] as well as in hardware-software co-design [11]. However, the description of the expected behavior is typically performed manually, which is both time-consuming and error-prone. First attempts to automate this process employed classical Natural Language Processing (NLP) techniques [12], but these approaches remain limited in their expressiveness and accuracy.
In parallel, Large Language Models (LLMs) have made remarkable progress and are increasingly being explored in the field of Electronic Design Automation (EDA) [13,14]. Their ability to interpret and generate complex textual descriptions makes them a promising technology to support BDD in hardware design.
In this paper, we apply LLM-based techniques to BDD for hardware. We demonstrate that, starting from a textual specification, an LLM can automatically generate high-level behavioral descriptions suitable for BDD workflows. As a case study, we show for an Arithmetic Logic Unit (ALU) that relevant scenarios can be generated directly by the LLM and subsequently simulated on the corresponding Verilog implementation.
A central element of BDD is the definition of scenarios that describe the expected system behavior in a structured and executable form. In practice, these scenarios are commonly written using the Gherkin language. A typical Gherkin feature file may look as follows:
Feature: User Login Scenario: Successful login with valid credentials Given the user is on the login page When the user enters valid credentials Then the user should see the dashboard Such scenarios must traditionally be crafted manually, a process that is both time-consuming and prone to inconsistencies or omissions, as noted in the introduction. Earlier attempts to automate scenario derivation relied on classical AI and NLP techniques [12]. However, these methods were limited in their ability to extract meaningful behavioral descriptions from non-trivial specifications and required substantial fine-tuning to achieve acceptable results.
With recent advances in NLP models, the generation of BDD scenarios can be significantly simplified and improved. In our approach, the initial textual specification of the hardware design is provided directly to a hybrid generation system. For this work, we employ ChatGPT-51 together with a lightweight local template engine. The prompting process is intentionally minimal, enabling the system to interpret the specification and produce suitable Gherkin scenarios without extensive engineering effort. A representative prompt is shown below:
Using this simple instruction, the LLM is able to translate the textual description into structured BDD scenarios that follow the Given-When-Then pattern. These generated scenarios serve as an effective starting point for hardware verification, reducing manual workload while increasing consistency and coverage.
To demonstrate the complete flow of our approach from textual specification to executable verification, we consider a 16-bit ALU. First, only an informal textual description of the intended behavior of the ALU is available. This mirrors common industrial scenarios, where specifications are written in natural language and must be manually translated into hardware and corresponding test scenarios. Using our LLM-based methodology, both the Verilog implementation and the associated BDD scenarios are automatically generated.
Based solely on the textual specification, the LLM generates a syntactically and semantically correct Verilog model of the ALU. This includes all arithmetic operations, status signals, and combinational logic. For illustration, the generated code for the ADD operation is shown below:
The generated Verilog demonstrates several noteworthy properties. First, it adheres to standard design conventions, such as explicit handling of carry propagation and correct two’s complement overflow detection. Second, it reflects Finally, we observed that the LLM-generated design was immediately compilable and simulatable without requiring manual debugging, which is an important indicator of practical usefulness.
In the next step, BDD scenarios are automatically derived from the same textual specification, ensuring consistency between the implementation and verification intent. These scenarios follow the Gherkin Given-When-Then structure an
This content is AI-processed based on open access ArXiv data.
