ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework

ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie* Hong Kong University of Science and Technology {qzhangcs, sliudx, yludf, mengming.li}@connect.ust.hk, eezhiyao@ust.hk Abstract—Power is a primary objective in modern processor design, requiring accurate yet efficient power modeling techniques. Architecture- level power models are necessary for early power optimization and design space exploration. However, classical analytical architecture-level power models (e.g., McPAT) suffer from significant inaccuracies. Emerging machine learning (ML)-based power models, despite their superior accuracy in research papers, are not widely adopted in the industry. In this work, we point out three inherent limitations of ML-based power models: unreliability, limited interpretability, and difficulty in usage. This work proposes a new analytical power modeling framework named ReadyPower, which is ready-for-use by being reliable, inter- pretable, and handy. We observe that the root cause of the low accuracy of classical analytical power models is the discrepancies between the real processor implementation and the processor’s analytical model. To bridge the discrepancies, we introduce architecture-level, implementation- level, and technology-level parameters into the widely adopted McPAT analytical model to build ReadyPower. The parameters at three different levels are decided in different ways. In our experiment, averaged across different training scenarios, ReadyPower achieves > 20% lower mean absolute percentage error (MAPE) and > 0.2 higher correlation coefficient R compared with the ML-based baselines, on both BOOM and XiangShan CPU architectures. I. INTRODUCTION Power is a primary design objective in modern processor design, requiring accurate yet efficient power modeling techniques. The standard power estimation process requires the full VLSI design flow—requiring Register-Transfer Level (RTL) implementation, fol- lowed by RTL simulation, logic synthesis, and gate-level power analysis with EDA tools [1]–[3]. While this process delivers high accuracy, it incurs substantial manpower and runtime, making it impractical for rapid design iterations. As a result, architecture-level power models are in high demand for early power optimization and design space exploration. There are two types of architecture- level power models: 1) conventional analytical models, and 2) recent machine learning (ML)-based models, as we introduce below. Analytical Power Model: Conventional architecture-level power models are analytical models, such as McPAT [4] and Wattch [5]. These models require engineers to meticulously characterize each microarchitectural component within a target processor [6]. As a result, they typically suffer from significant inaccuracies when applied to new architectures, as indicated in many existing studies [6]. ML-based Power Model: In recent years, machine learning (ML)- based architecture-level power models emerged to address the accu- racy limitations of traditional analytical models. These data-driven models construct either black-box [7] or gray-box [8] representations of power consumption. The models are trained with known processor design configurations with ground-truth power values. When trained with appropriate data, these ML-based models have demonstrated high accuracy compared to analytical models. Rethinking: why are ML-based models not widely adopted? Despite the clearly superior accuracy of recent ML-based power models [7]–[9], unexpectedly, we notice that these new ML-based methods are not widely adopted in the industry. Instead, architects continue to utilize analytical models such as McPAT, although sub- stantial engineering effort is required to fix the inaccuracies. This observation motivates this work, which starts with rethinking the problem of existing research on ML-based power models. We point out three inherent limitations of ML-based power models below. 1) Unreliability: ML models are inherently weak at extrapolation, since ML models are performing interpolation1 based on training data. As a result, ML models can become extremely unreliable when the testing data falls out of the distribution of training data. For instance, models trained only on small processor *Corresponding Author 1Interpolation is performing inference within the range (i.e., distribution) of the known training data, while extrapolation goes beyond the range. Fig. 1: The ReadyPower framework. ReadyPower fixes the discrepancies between real processor implementation and classical power models. It introduces new architecturally interpretable parameters at the architecture, implementation, and technology levels within the analytical framework. configurations will be highly inaccurate when applied to large configurations, and vice versa2. 2) Limited Interpretability: ML-based power models are inher- ently black-box, pre

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