Quantum circuit design is a key bottleneck for practical quantum machine learning on complex, real-world data. We present an automated framework that discovers and refines variational quantum circuits (VQCs) using graph-based Bayesian optimization with a graph neural network (GNN) surrogate. Circuits are represented as graphs and mutated and selected via an expected improvement acquisition function informed by surrogate uncertainty with Monte Carlo dropout. Candidate circuits are evaluated with a hybrid quantum-classical variational classifier on the next generation firewall telemetry and network internet of things (NF-ToN-IoT-V2) cybersecurity dataset, after feature selection and scaling for quantum embedding. We benchmark our pipeline against an MLP-based surrogate, random search, and greedy GNN selection. The GNN-guided optimizer consistently finds circuits with lower complexity and competitive or superior classification accuracy compared to all baselines. Robustness is assessed via a noise study across standard quantum noise channels, including amplitude damping, phase damping, thermal relaxation, depolarizing, and readout bit flip noise. The implementation is fully reproducible, with time benchmarking and export of best found circuits, providing a scalable and interpretable route to automated quantum circuit discovery.
Variational quantum circuits (VQCs) have become a central computational primitive for many near-term quantum algorithms, including variational quantum classifier (VQ-C), Quantum Neural Network (QNN), quantum generative adversarial network (QGAN), variational quantum eigensolver (VQE), and quantum approximate optimization algorithm (QAOA) [5, 6, 9, 10, 22-24, 26-29, 41, 45]. The performance of a VQC depends critically on both its parameter values and architectural design, defined by the arrangement, type, and connectivity of quantum gates within the circuit [1,19,25,46]. Designing VQC architectures for noisy intermediate-scale quantum (NISQ) devices thus presents a high-dimensional, non-convex optimization problem, with a combinatorial search space that quickly renders brute-force or exhaustive enumeration intractable as the number of qubits and circuit depth increase [48,56].
To address this challenge, recent work on automated quantum architecture search has adopted techniques from classical neural architecture search (NAS) [8,43], evolutionary strategies, and blackbox optimization to systematically explore the quantum circuit design space [12,13,17,30,49,54]. In particular, Bayesian optimization (BO) provides a principled and sample-efficient framework for global optimization of expensive-to-evaluate objectives, making it highly suitable for quantum circuit architecture search, where each candidate must be validated via simulation or hardware execution [32,40,44,47,53].
One of the main challenges in BO lies in constructing a surrogate model that can both accurately predict a circuit’s performance and provide calibrated epistemic (model) uncertainty that shrinks with data, as opposed to aleatoric (noise) uncertainty [33]. Classical BO typically employs Gaussian processes [4], while simple multilayer perceptrons (MLPs) require fixed-size, hand-crafted vectors and cannot exploit the directed acyclic graph (DAG) structure of quantum circuits, where nodes represent gate operations and edges capture temporal or qubit dependencies. As illustrated in Fig. 1, two circuits may share the same aggregate scalars (e.g., total gates, depth) yet differ substantially in topology and function-information preserved only in their graph representations. This limitation motivates the use of structure-aware surrogates, such as graph neural networks (GNNs), which are designed to process variable-sized, structured data and can naturally represent quantum circuits as graphs-nodes corresponding to gate operations and edges capturing connectivity or temporal dependencies [37,55]. Among them, the Graph Isomorphism Networks (GIN) offer provably strong graph discrimination power (Weisfeiler-Lehman test level) and have demonstrated superior ranking and generalization performance on graph-structured tasks [52]. When equipped with Monte Carlo dropout, GNN-based surrogates can provide both accurate performance predictions and calibrated uncertainty estimates, enabling acquisition strategies such as Expected Improvement (EI) to more effectively balance exploration and exploitation in the BO loop [16].
In this work, we present a graph-based BO pipeline for automated quantum circuit architecture search, targeted toward hybrid quantum-classical classification tasks. Automated quantum circuit search typically suffers from five issues: (i) collapsed architectural differences in fixed-vector surrogates (gate counts/depth collapse Simple Circuit q 0 q 1 q 2 H 0.
Figure 1: Comparison of two quantum circuits with their feature vectors and graph representations. While aggregate scalar features (e.g., gate counts, depth) can appear similar, the graph encoding preserves topological and dependency information critical for distinguishing circuit function. This motivates the use of graph neural networks (GNNs) as structure-aware surrogates in quantum circuit optimization.
non-isomorphic circuits to similar features), (ii) uncertainty miscalibration that destabilizes exploration-exploitation in BO, (iii) hardware insensitivity to device constraints, where architecture selection ignores routing overheads (extra CX/SWAP) that appear after transpilation, (iv) noise insensitivity to realistic 𝑇 1 /𝑇 2 and readout effects, and (v) search bloat toward deep, two-qubit-heavy layouts. Our method addresses these challenges through a unified pipeline comprising: a structure-aware GIN surrogate with MC-dropout for calibrated epistemic uncertainty, a tempered, cost and noise-aware expected improvement, and a transpiler-aware selection strategy that mitigates the simulator-device gap. The full pipeline is evaluated under comprehensive noise studies and reproducible experimental protocols.
Specifically, our contributions are as follows:
(1) Structure-aware surrogate for VQCs. We encode circuits as graphs with temporal and shared-qubit edges and train a lightweight GIN surrogate that predicts performance and uncertainty (via MC dropout), improving ranking stability
This content is AI-processed based on open access ArXiv data.
