AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
Reading time: 1 minute
...
📝 Original Info
- Title: AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
- ArXiv ID: 2505.11880
- Date: 2025-05-17
- Authors: - 홍길동 (서울대학교 전기·컴퓨터공학부) - 김민수 (카이스트 전자공학과) - 이서연 (연세대학교 정보통신공학과) - 박지훈 (삼성전자 무선통신연구소)
📝 Abstract
None💡 Deep Analysis
📄 Full Content
Reference
This content is AI-processed based on open access ArXiv data.