A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions

📝 Original Info

• Title: A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions
• ArXiv ID: 2504.01672
• Date: 2025-04-02
• Authors: ** 정보 없음 (제공된 텍스트에 저자 정보가 포함되어 있지 않음) **

📝 Abstract

At the intersection between traditional CPU architectures and more specialized options such as FPGAs or ASICs lies the family of reconfigurable hardware architectures, termed Coarse-Grained Reconfigurable Arrays (CGRAs). CGRAs are composed of a 2-dimensional array of processing elements (PE), tightly integrated with each other, each capable of performing arithmetic and logic operations. The vast design space of CGRA implementations poses a challenge, which calls for fast exploration tools to prune it in advance of time-consuming syntheses. The proposed tool aims to simplify this process by simulating kernel execution and providing a characterization framework. The estimator returns energy and latency values otherwise only available through a time-consuming post-synthesis simulation, allowing for instantaneous comparative analysis between different kernels and hardware configurations.

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