In this paper, we proposed a non-uniform power delivery network (PDN) synthesis methodology. It first constructs initial PDN using uniform approach. Then preliminary power integrity analysis is performed to derive IR-safe candidate window. Congestion map is obtained based global route congestion estimation. A self-adaptive non-uniform PDN synthesis is then performed to globally and locally optimize PDN over selected regions. The PDN synthesis is congestion-driven and IR- guarded. Experimental results show significant timing important in trade-off small PDN length reduction with no EM/IR impact. We further explored potential power savings using our non-uniform PDN synthesis methodology.
Morden semiconductor integrated circuit design has been scaling drastically into nanometer feature size range. To achieve better performance, higher power density and more routing resource is required. Both post challenges to on-chip power delivery network (PDN) design, which needs to deliver power supply to every transistor on die. The PDN needs to meet electromigration (EM) and IR limit to guarantee power integrity of a chip [1]. EM limit requires current density through each PDN wire segment and via to be lower than a threshold value, while IR limit requires the voltage drop when reaching transistor source node. Failure to satisfy power integrity will lead to reliability issues or chip malfunction [2]. Meanwhile, wire RC delay has become increasingly significant and dominants the propagation delay of a large portion of critical paths [3]; therefore, either more and more routing layers are added to increase routing resource or PDN resource needs to be carefully assigned to save space for signal routing. Thus, efficient PDN design and optimization is the key to deliver successful higher performance chip in current and future technology nodes.
In this paper we propose a non-uniform PDN design methodology that optimizes PDN both globally and locally that occupies less routing resource compared to traditional PDN design. The saved routing space helps to improve signal routing in congested area and achieve better timing results. Further exploration shows that potential power saving can be obtained by leakage reduction through cell threshold voltage optimization.
In traditional PDN design, designers first estimate the chip power density, current density and IR drop based on technology information, such as cell power, sheet resistance, etc. Then a uniform PDN is designed to meet the power integrity requirement based on estimation. A few iterations are performed to modify the initial version to eventually close EM/IR limit [4]. PDN design and optimization technique has been widely investigated by researchers. In [5], S. Kose proposed a power grid design based on effective resistance. Z. S. Zheng provided a tradeoff optimization with voltage regulation in [6]. While in [7], T. Hayashi investigated power grid optimization algorithm based on manufacturing cost restriction. However, there are a few limitations to previous conventional approach: (1) since cell density is not uniformly distributed, the power density estimation is usually over pessimistic to cover possible local power hotspots; (2) since PDN is designed first before place and route happens, PDN designers have no knowledge how the actual power distribution look like, thus it is impossible to apply non-uniform style PDN to optimize for different design blocks. Figure 1 shows a typical IR drop distribution and how PDN designed for high percentile power density could be over-designed for low percentile power density. Often, temperature and variation effects are included in the analysis to obtain more realistic results [9]. The two limitations implies inevitable over-design of traditional style PDN. To overcome this shortage, we propose an EM/IRaware and congestion-driven non-uniform PDN design methodology that globally meets power integrity requirement and locally optimizes signal routing resource. To our best knowledge, this is the first systematic work to address the nonuniform style PDN synthesis.
The non-uniform PDN methodology starts with traditional uniform PDN construction. The uniform PDN is fed into regular place, clock synthesis and post-clock optimization. Then a preliminary EM/IR analysis is run on a pre-route database. Based on the analysis results, we identify design regions that are IR safe as potential non-uniform PDN modification candidate. A routing congestion map based on global route engine is used to drive the actual non-uniform PDN synthesis. In later sections, we discuss in detail the candidate selection, non-uniform PDN synthesis and timing/power benefits using our proposed methodology.
In our approach, the entire design is divided into unit size windows (e.g. 20um x 20um). Preliminary EM/IR result and routing congestion map for each window is derived and used as basic metrics for candidate selection.
The reasoning for running a preliminary EM/IR analysis on a pre-route database is that cell placement are largely determined by the time post-clock optimization is done, so the result correlates well with the final sign-off EM/IR analysis. It is critical to avoid reduce PDN over EM/IR critical regions as reliability is a key factor to guarantee quality design [8].Besides, although non-uniform PDN synthesis can be introduced after route, during engineering-change-order (ECO) stage, it will be best to interfere before route stage for router to best leverage its benefits. Later in this section, we will discuss how fast IR analysis and congestion estimation is done for each unit size window.
To determining if a window is IR-safe, we u
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