Efficient reconfigurable regions management method for adaptive and dynamic FPGA based systems

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📝 Original Info

  • Title: Efficient reconfigurable regions management method for adaptive and dynamic FPGA based systems
  • ArXiv ID: 1803.03331
  • Date: 2015-03-18
  • Authors: : Aljazzaf, A.; Lysaght, D.; Hong, J. et al.

📝 Abstract

Adaptive systems based on field programmable gate array (FPGA) architectures can greatly benefi t fro m th e high degree of flexibility offered by dynamic partial reconfiguration (DPR). By using this technique, hardware tasks can be loaded and reloaded on demand depending on the system requirements. In this paper, we propose to use the DPR for dynamic and adaptive implementation of a video cut detection application based on the MPEG-7 color structure descriptor (CSD). In the proposed implementation, different scenarios have been tested. Depending on the application and the system requirements, the CSD module can be loaded at any time with variable module size (corresponding to different version of the CSD) and allocated in different possible reconfigurable regions. Such implementation entails many problems related to communication, relocation and reconfigurable region management. We will demonstrate how we have made this implementation successful through the use of an appropriate design method. This method was proposed to support the management of variable-size hardware tasks on DPR FPGAs based adaptive systems. It permits to efficiently handle the reconfigurable area and to relocate the reconfigurable modules in different possible regions. The implementation results for the considered application show an important optimization in terms of configuration time (until 66 %) and memory storage (until 87 %) and an efficient hardware resources utilization rate (until 90%).

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DPR technique offers the ability to modify the configuration (circuit structure) of an FPGA part, while the rest of the device continues working without interruption (Hong et al. 2014;Lysaght et al. 2006). In DPR systems, the architecture is partitioned into static and partial reconfigurable regions (PRR). In order to enable an application to change the PRR structure, a set of configurations, known as partial reconfigurable modules (PRMs), is required. The latter will be substituted and placed in a predefined PRR on the FPGA.

FPGA-based DPR is greatly appropriate choice for systems needing a high degree of flexibility. This promising technique can be applied to deal with: lack of available resources, reduction of energy consumption, system adaptability and system reliability. The following situations can benefit from DPR: • Available resources are smaller than system’s resource requirement. • Necessity of reducing system energy consumption.

• The application is composed of multiple independent and time exclusive tasks (can be implemented sequentially by sharing the same hardware resources). • Some hardware resources are not always needed.

• System used for multiple application contexts • System supporting components upgrade (with improved or updated versions).

• System functions have to be changed depending on the application environment.

One of the key challenges in DPR FPGA based architectures design is the reconfiguration and the PRR management: relocation, communication, etc. In this paper, we propose a dynamic and adaptive implementation of a video analysis application, while fixing the problems related to communication, relocation and reconfigurable region management. We propose a dynamic implementation of a cut detection application based on the MPEG-7 CSD. Depending on the application and the system requirements, the CSD module can be loaded at any time with variable module size (corresponding to different quantization levels) and relocated in different possible reconfigurable regions. The use of the DPR technique with partial bitstream relocationpresents many benefits in our application such as: the possibility of relocating the bitstream generated for a specific PRR on different other ones, eliminating the need to multiple PRB for the same hardware task, reducing the amount of memory used to store partial bitstreams and allowing runtime bitstreams placement. However implementation of this technique entails many problems related to communication and area management (related to variable size modules). In fact, the same communication constraints must be maintained between DRRs for the different related PRMs. Also, for variable size modules occupying the same region, an appropriate management strategy is necessary to increase the area use and the configuration time efficiency. To address these problems, a method supporting variable-sized hardware tasks will be proposed and applied for the considered application.

The rest of this paper is organized as follows: Section 2 is dedicated to the application context description and the problem formulation. The DPR application scenario and the different problems involved will be also addressed in this section. In section 3, we will describe the considered application of video cut detection based on the CSD and the reconfigurable hardware modules design. The proposed method will be detailed in Section 4. Section 5 will be dedicated to describe the experimental results obtained during the CSD based cut detector approach.

Modern multimedia systems are characterized by a rich set of services from which the user can easily make a choice to switch between the different given ones. It can also add new services or substitute the existing ones according to its preference. In this case, quality of Services (QoS) is of a big importance; it is used as a distinct factor between similar services (Aljazzaf, 2015). To support such functionalities and the high requirements in terms of multi-processing capacity, portability and consumption, the use of adequate hardware systems with high level of adaptability becomes necessary. In this context, the DPR utilization can be a very interesting solution. An appropriate application of this technique permits to support complex scenarios of adaptive and dynamic multimedia treatments implementation.

The considered application scenario in this work is illustrated in Figure 1. Given a set of multimedia treatments, an FPGA partitioned into dynamically reconfigurable regions, and relative to the choice made by the user, different modules treatments will be loaded into the FPGA. These modules can be allocated in different reconfigurable regions, depending on the system configuration at the moment of the new service selection. Also, adaptive version of different treatment modules can be loaded depending on the application environment and system requirements. These modules are given with different service qualities and physical sizes.

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