Reversible logic allows low power dissipating circuit design and founds its application in cryptography, digital signal processing, quantum and optical information processing. This paper presents a novel quantum cost efficient reversible BCD adder for nanotechnology based systems using PFAG gate. It has been demonstrated that the proposed design offers less hardware complexity and requires minimum number of garbage outputs than the existing counterparts. The remarkable property of the proposed designs is that its quantum realization is given in NMR technology.
Irreversible logic circuits dissipate heat in the amount of kT ln2 Joule for every bit of information that is lost irrespective of their implementation technologies, where k is the Boltzmann constant and T is the operating temperature [1]. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit naturally takes care of heating because it implements only the functions that have one-toone mapping between its input and output vectors. Therefore reversible logic design becomes one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. According to [2] zero energy dissipation would be possible only if the network consists of reversible gates. Thus reversibility will become an essential property in future circuit design.
Reversible logic imposes many design constraints that need to be either ensured or optimized for implementing any particular Boolean functions [3][4][5]. Firstly, in reversible logic circuit the number of inputs must be equal to the number of outputs. Secondly, for each input pattern there must be a unique output pattern. Thirdly, each output will be used only once, that is, no fan out is allowed. Finally, the resulting circuit must be acyclic. Any reversible logic design should minimize the followings [6]:
• Garbages: outputs that are not used as primary outputs are termed as garbages.
• Constants: constants are the input lines that are either set to zero(0) or one (1) in the circuit’s input side • Gate Count: number of gates used to realize the system Manuscript received July 6, 2011 Md. Saiful Islam is with the Institute of Information Technology, University of Dhaka, Bangladesh. (e-mail: saiful@iit.du.ac.bd).
Mohd. Zulfiquar Hafiz is with the Institute of Information Technology, University of Dhaka, Bangladesh. (e-mail: jewel@univdhaka.edu).
Zerina Begum is with the Institute of Information Technology, University of Dhaka, Bangladesh. (e-mail: zerin@univdhaka.edu).
• Hardware Complexity: refers to the number of basic gates (NOT, AND and EXOR gate) used to synthesize the given function • Quantum Costs: quantum realization cost of the design in any particular nanotechnology This paper presents a novel quantum cost efficient reversible logic implementation of BCD adder. The design includes PFAG as its basic building block proposed in [6]. The quantum realization cost of PFAG in NMR technology is 8 [6]. The proposed reversible BCD adder is optimized in terms of gate count and quantum costs.
A gate or a circuit is called reversible if there is a one-toone correspondence between its input and output assignments. Any reversible circuit realizes only the function that is reversible. There exist many reversible gates in the literature. Among them Feynman gate, FG [7], Peres gate, PG [8], Toffoli gate, TG [9], Fredkin gate, FRG [10] and Khan gate, NG [11] are mostly common (Fig. 12345). The quantum realizations of all these gates are not available in the literature. Only FG, PG, TG, and FRG have been realized in nanotechnology. The detail cost of a reversible gate depends on any particular realization technology of quantum logic. Every permutation quantum gate is built from 11 (inverter) and 22 (FG) quantum primitives and its cost is calculated as a total sum of 2*2 gates. The quantum realization cost of FRG and TG is 5. The quantum cost of PG is 4 and it is the cheapest in terms of quantum realization cost [5].
Full adder is the fundamental building block of many computational units. The anticipated paradigm shift logic compatible with optical and quantum requires compatible adder implementations. Minimization of reversible fulladder circuits and their implementation issues has been discussed in [3][4][5]. It has been shown that a full adder circuit can be realized with at least two garbage outputs and one constant-input [5].
It has been assumed that full adder circuit that can work singly as a reversible full-adder unit will be beneficial to the quantum realization of other complex systems. The family of reversible full adder gates are PFAG gate [6], TSG gate [12], MKG gate [13] and HNG gate [14] (Fig. 6789). The quantum realizations of all these reversible full adder gate units are not available in the literature. Only PFAG has been realized in NMR nanotechnology. The quantum cost of PFAG is 8 [6]. It has also been demonstrated in [6] that PFAG is better than TSG, MKG and HNG in terms of hardware complexity. This study presents two BCD adder implementations realized using PFAG gates as its fundamental building block proposed in [6]. The designs are shown in Fig. 11 and Fig. 12. The proposed BCD adders have two reversible 4-bit parallel adders, which require total eight PFAG gates. Furthermore, two extra PFAG gates and one PG gate are required for implementing the correctio
This content is AI-processed based on open access ArXiv data.