This paper presents a novel repeater insertion algorithm for interconnect power minimization. The novelty of our approach is in the judicious integration of an analytical solver and a dynamic programming based method. Specifically, the analytical solver chooses a concise repeater library and a small set of repeater location candidates such that the dynamic programming algorithm can be performed fast with little degradation of the solution quality. In comparison with previously reported repeater insertion schemes, within comparable runtimes, our approach achieves up to 37% higher power savings. Moreover, for the same design quality, our scheme attains a speedup of two orders of magnitude.
This paper presents a novel hybrid repeater insertion technique for low-power global interconnect designs. Given a two-pin interconnect and its timing budget, our algorithm derives the number of repeaters, and the width and location of each repeater so that the timing constraint is satisfied and power dissipation is minimized. The hybrid nature of our scheme stems from its judicious combination of an analytical repeater insertion solver and a dynamic programming (DP) based approach. Specifically, our algorithm proceeds in three steps. First, an initial repeater insertion solution is derived using DP with a very coarse repeater library. Second, an analytical procedure is applied to refine the initial solution and derive a new repeater library and a set of location candidates that fit the current design. Finally, the DP algorithm is repeated with the new library and location set for the low-power repeater insertion solution.
Our hybrid algorithm maintains the advantages of both analytical and DP-based schemes, producing high-quality interconnect designs efficiently. Furthermore, it is highly practical due to the adoption of a realistic interconnect model. Specifically, the interconnects are represented as a sequence of wire segments with fixed lengths and distinct RC characteristics, as derived from a routing procedure. Moreover, our algorithm can handle forbidden zones, i.e., parts of interconnects through macrocells in which no repeater can be placed, and is thus applicable to nets routed in real design scenarios.
We have implemented our repeater insertion algorithm into a software tool, called RIP, and applied it to the de-sign of low-power global interconnects. In comparison with the conventional DP algorithms, our scheme achieves power reductions of up to 37% with comparable runtimes. Moreover, for the same design quality, RIP achieves shorter runtimes by two orders of magnitude.
The remainder of the paper is organized as follows. Section 2 describes previous research on repeater insertion. The problem of low-power repeater insertion for multi-layer two-pin interconnects is formulated in Section 3. In Section 4, analytical constraints on the repeater widths and locations are derived that must be satisfied to minimize repeater power dissipation. Our algorithm is presented in Section 5. Section 6 presents our experimental results. Section 7 summarizes our paper.
Extensive work on repeater insertion has appeared in the literature [4,19]. Repeater insertion has been applied to interconnect designs with various objectives such as delay minimization [3,12,17] and power minimization [5,10,13,15,16]. Several circuit models have been proposed to compute the delay and power dissipation of repeaters such as the switch-level RC model [8] and moment matching model [1]. In analytical repeater insertion schemes, the optimization objectives are described using analytical functions of repeater width and location. The optimal repeater insertion solutions can be derived by setting the derivatives of these functions to zero and solving the ensuing equations [6,7]. Analytical schemes assume that the repeater widths and/or locations can be continuously changed. In actual designs, however, repeater widths are discrete due to layout design rules. In addition, the repeater locations are restricted to areas not occupied by circuit blocks. Consequently, when practical interconnects are considered, the analytical objective functions become very complex or even intractable.
To address the limitation of analytical schemes, a repeater insertion algorithm based on DP was proposed in [11] and improved in [20] for interconnect delay minimization. This algorithm has been modified for interconnect power reduction [14,18,21]. In these DP schemes, the possible widths and locations of the repeaters are discrete and finite. The algorithms choose the best solution out of all the possibilities. As a result, the efficiency of the DP schemes may be significantly affected by the given repeater library and potential repeater locations. Specifically, if the allowable repeater widths and locations are too limited, the quality of the interconnect may degrade substantially. On the other hand, when the numbers of repeater widths and locations are large, the DP algorithms become very timeconsuming [14].
DP algorithms perform well for interconnect delay reduction, since the delay of a min-delay interconnect design is insensitive to its repeater widths and locations [9]. Consequently, a small-size coarse-granularity repeater library can be derived and applied to all interconnect designs with limited performance loss [2]. However, when power reduction is considered, i.e., the problem addressed in this paper, DP schemes become less effective. Power dissipation of repeaters is sensitive to repeater widths, since at a first order approximation, gate capacitance depends linearly on repeater widths. Consequently, fine granularities are needed for repeater w
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