New Schemes for Self-Testing RAM

March algorithms are commonly and widely used to test the units of random access memory (RAM). In [1] it is proposed a formal notation of the mathematical presentation of March-test algorithm. An example of such notation is the following: MarchA= {c(w0); ⇑(r0w1); ⇓(r1w0)}, where the symbols {⇑, ⇓, c} refer to traversing the address space of a memory (respectively up, down or don't care address order). The operations w d and r d refer to write or read logic value: d∈{0, 1}.

A new self-test RAM methodology (technique), named pseudo-ring testing (PRT), was proposed recently [2]. In this paper a retrospectives and some new schemes of this technique for a wide type of RAM are presented. PRT schemes will be referred to bit-oriented (BOM) and wordoriented memory (WOM). The cell size m of the BOM is equal to 1 and for WOM is m>1. Some algorithmic features for single and multi-port memories also will be presented.

The PR-testing consists of some, so-called, π-test iterations. In particular case, such iteration can be shown by the equation:

where {…} signifies a sub-iteration that performs the included operations. Index i refers to the address cell of a memory array. Symbol ⊕ signs the operation sum modulo In the next step first and second read-operations read from two neighboring memory cells and the third writeoperation writes the sum modulo 2 (XOR) of the read values to the next (third) memory array cell. Next set of operations will read second and third memory cells and writes results of its logical contains to the next, forth, memory cell, and so on. This enables an automatic generation of the test data background (TDB).

At the end of π-test iteration the final state Fin is compared with expected one Fin * . The state Fin * can be estimated a priori, because π-test iteration has an adequate linear automaton model. This model is well known as Linear Feedback Shift Register (LFSR). The LFSR can be bit-oriented, when the stage contains one bit, and wordoriented, when the stage contains more than one bit.

where k is the number of linear automaton register stages; a i are the Galois field (GF) elements.

The PRT technique can be illustrated as a transition of a (virtual) linear automaton in the space of the cells memory array. Figure 1 illustrates the expected states of the BOM and WOM cells after iterative execution of subiterations (1). For the scheme of figure 1,b the wordoriented virtual LFSR is defined by polynomial g(x)=1+2x+2x 2 that is irreducible in the field GF(2 4 ); size of word m is equal to 4. In each sub-iteration (1) is performed the multiplication and sum modulo p(z), where Multiplication over Galois field extensions is a more complex operation. It’s proposed an algorithm to design the optimal scheme of multiplication by a constant in GF.

Multiplier by a constant contains only XOR-gates and can be implemented inherently in the memory circuit.

If the memory array size is multiple by the period of LFSR then virtual automaton will return to the initial state at the end of the test iteration (see figure 1,b). So, the πtest quality will be estimated by comparing initial Init and final Fin states of LFSR.

For the WOM there are intra-word faults that can be tested by parallel application of a π-testing for BOM. In this case it is supposed that there are m independent bitoriented linear automatons. For all automatons the read and write operations are executed simultaneously. To detect the intra-word faults two different π-testing can be performed: (1) with parallel or (2) with random trajectories. The trajectory is controlled by a small hardware overhead that can be programmed externally.

The quality (faults coverage) of PRT RAM can be strongly estimated by mathematical analysis of LFSR behavior in the space of a memory array. Defects in memory array are (generally) due to shorts and opens in memory cells, address decoder and read/write logic. These defects can be modeled as single and multi-cell memory faults [1]. There are three factors that influence on π-test quality and they can be used to control the π-testing: 1 -LFSR structure that is determined by generator polynomial structure; 2 -initial values for the π-test iterations; and 3 -LFSR trajectory that can be random, where address of memory cells are randomly selected, or deterministic, where address cells are selected in an increasing or a decreasing mode.

Applying Markov chain analysis it was shown that πtest iteration has a high resolution for most memory faults. Also, the combinatorial analysis of RAM π-testing has shown that it is necessary at least 3 test iteration to cover all specified faults. In [2] was proved that all single and multi-cell memory faults are detected in 3 π-test iterations with a specific TDB. This result is valid for bit-oriented as well as for word-oriented memories. The time complexity of π-test iteration for single port RAM is order O(3n).

This time can be reduced in the case of multi-port RAM PRT.

Two-port (2

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