The hybrid hiding encryption algorithm, as its name implies, embraces concepts from both steganography and cryptography. In this exertion, an improved micro-architecture Field Programmable Gate Array (FPGA) implementation of this algorithm is presented. This design overcomes the observed limitations of a previously-designed micro-architecture. These observed limitations are: no exploitation of the possibility of parallel bit replacement, and the fact that the input plaintext was encrypted serially, which caused a dependency between the throughput and the nature of the used secret key. This dependency can be viewed by some as vulnerability in the security of the implemented micro-architecture. The proposed modified micro-architecture is constructed using five basic modules. These modules are; the message cache, the message alignment module, the key cache, the comparator, and at last the encryption module. In this work, we provide comprehensive simulation and implementation results. These are: the timing diagrams, the post-implementation timing and routing reports, and finally the floor plan. Moreover, a detailed comparison with other FPGA implementations is made available and discussed.
In this work, we present an FPGA-based microarchitecture implementation of a modified version of the encryption algorithm entitled "Hybrid Hiding Encryption Algorithm (HHEA)" [SHAAR03]. In the basic version of this algorithm, no conventional substitution and translation operations on the plaintext characters are used. It rather uses simple plaintext hiding in a random bit string called the hiding vector. The name "Hybrid" is used to show that this encryption algorithm has built-in features that are inherited from data hiding techniques or "Steganography". As a matter of fact, one can use the micro-architecture for both steganography and cryptography depending on the user approach and the proper selection of the key. The basic version of this algorithm was previously implemented, as shown in reference [SAEB04a]. However, this approach did not exploit the possibility of parallel bit replacement. Furthermore, the input plaintext was encrypted serially, which caused some dependency between the throughput and the nature of the key. This dependency can be viewed by some as vulnerability in the security of the implemented micro-architecture. Based on these observations and to eliminate certain types of cipher attacks, we decided to present a modified algorithm and its accompanying micro-architecture that overcomes such limitations. The modified design eliminates the dependency between the micro-architecture throughput and the key. It also provides a significant performance improvement by fully exploiting the inherited parallelism originated by the algorithm. Moreover, the modified version escapes the chosen-plaintext attacks. In the next few sections we discuss the modified algorithm, the building blocks of the proposed improved microarchitecture along with details of its operation, the simulation and implementation results. The details of the carried out simulations, timing, routing reports and the floor plan are completely provided in the given appendix. Moreover, we present a comparison with other implementations of a selected group of encryption algorithms [SAEB02], [SAEB02].
In the following few lines, we provide a summary of the MHHEA algorithm [SHAAR03]. The aim of the algorithm is hiding a number of bits from plain text message (M) into an N-bit long random vector (V). The locations of the hidden bits are determined by the key (K).
Algorithm MMHHEA [Given a plain text message M , key matrix K Lx2 , scrambled key matrix KN Lx2 where i =0,…., L; L 15
The aim of the algorithm is hiding a number of bits from plain text message (M) into a random vector (V) of bits. The locations of the hidden bits are determined by the key K Lx2 ] Input: M, K Lx2 , Output: encrypted file Algorithm Body: i: =0, m:=0 M[0]: =first digit in M file while (M[m] EOF) [EOF: End Of File] i: = i mod L Generate 16-bit randomly and set them in V Vector if (K i,1 K i,2 ) then z: =Ki,1 Ki,1: =Ki,2 K i,2 : =z // Scramble the hiding location using the high order bits of the hiding vector KNi,1:=V[Ki,2+8 down to Ki,1+8] XOR Ki,1 KNi,2:= KNi,1+(Ki,2-Ki,1) mod 8 if (KN i,1 KN i,2 ) then z: =KN i,1 KNi,1: =KNi,2 KNi,2: =z // Scramble the message bits using the original key q:=0 for j= KN i,1 to KN i,2 q:=q mod 3
m: =m+1; next m in M file q:=q+1 end do next j Save V in output file i: =i+1 end while; End algorithm.
In this algorithm, we have scrambled the location and the message to overcome constant chosen-plaintext attack.
In this section we describe the micro-architecture with its operation details using a finite state machine approach (FSM). The FSM, shown in Figure 1, illustrates the conceptual required hardware modules and the elements of the design of the control unit. The machine operation takes place through six basic states. These are summarized as follows. The initial state “Init” holds back the execution of the successive states until the “Go” signal is triggered and furthermore resets all hardware modules. In the following state “LMsg”, the 32-bit input plaintext is buffered for the other modules to operate on. The key is buffered into sixteen four-bit pairs of registers in the “LKey” state. The key is saved in pairs of integers. One part of the key is XOR-ed with a part of the random vector V as described in the algorithm. After the scrambling of the key, the new key points to the locations of the substitution procedure as depicted in Figure 2. In a previous work [SAEB04a], this procedure was performed serially where in each cycle one bit is replaced until the entire range from the left to right key is covered. However, we aim at designing a modified architecture that replaces the whole number of bits determined by the key in parallel rather in serial to improve the overall performance. The location of the replaced bits is determined randomly based on the generated sub-key. In this respect, two design alternatives are possible. In the first one, a variable connection between the register containing the random hiding vector and t
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