Reduction in power consumption has become a major criterion of design in modern ICs. One such scheme to reduce power consumption by an IC is the use of multiple power supplies for critical and non-critical paths. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of power grid hierarchy. This paper describes about three-voltage supply power distribution systems. The noise at one power supply can propagate to the other power supply, causing power and signal integrity problems in the overall system. Effects such as anti-resonance and remedies for these effects are studied. Impedance of the three-voltage supply power distribution system is calculated in terms of RLC-model of decoupling capacitors. Further the obtained impedance depends on the frequency; hence brief frequency analysis of impedance is done.
Power has become one of the most important paradigms of design convergence in 45nm and not the performance [2]. This unconventional change has occurred due to the increasing demand for portable applications. A portable application makes use of battery-powered systems and thus appends a constraint of battery life before the designers. Although there has been substantial development in the increase of battery life, the stringent increase doesn't seem to be eminent [7]. Another reason for power becoming a concerning issue is the dissipation levels in highperformance computing using complex architectures. Power consumption in Intel processors has increased exponentially with the generations of process technologies [2]. Recent results show that a 1kg NiCd battery can support a Pentium 4 for less than an 1 hour whereas it can sustain a Centrino notebook for >3 hours. This reflects that reducing power dissipation can increment the overall performance of the system.
In the field of embedded systems, cropping of power consumption has always been a critical design issue. The easiest and effective way to accomplish reduction in power consumption by a particular circuit is to reduce its voltage supply level. Nevertheless any reduction in the supply voltage gives rise to propagation delays in the circuit. One of the techniques to compensate the propagation delays in circuits is shortening the critical paths in the data-path using behavioral transformations such as parallelization and pipelining. However the resulting circuit consumes lower average power while meeting the global throughput constraint at the cost of increased overhead circuit area.
In recent times, the use of multiple on-chip supply voltages has become an attractive technique to reduce the power consumption without causing any delays. The trick here is to allow the modules present at critical paths to use the highest voltage level and the modules residing on noncritical paths to use lower voltages. Delivering the modules on the critical paths with higher voltage satisfies the target timing constraints and supplying lower voltages to the modules present at non-critical paths reduces the energy consumption of the circuit. This scheme tends to result in smaller area overhead compared with the parallel architectures. In this whole process the system frequency is not affected. Practically a system with multiple voltage supplies faces certain problems such as multiple voltage scheduling [6]. Though having multiple voltage supplies on a chip appears attractive, there is a trade-off between cost and area. Hence the availability of two to three voltage supplies is realistic.
This paper is organized as follows. Section II describes about general overview about power distribution networks. Prior work on two-voltage supplies power distribution networks is discussed in detail in Section III. Section IV discusses about proposed three-voltage supply systems and Section V deals with Anti-resonance effects of decoupling capacitors. Some specific conclusions are summarized in Section IV.
The Power distribution network in a chip consists of chip level power distribution with thin-oxide decoupling capacitors, the package level power distribution with planes and mid frequency decoupling capacitors and board level power distribution with planes, low-frequency decoupling capacitors and voltage regulator module. With all these parameters involved in drawing, the design of power distribution system has become an increasingly difficult challenge in modern CMOS circuits [5].
Power distribution system plays a major role in determining the power consumption of the whole circuit. In a design of most microprocessors or ASIC chips, the target market sets the operating frequency. The timing constraints in the chip are in turn set by the operating frequency. Designers need to optimize the design to reduce the power consumption with the specified timing constraints. If the supply voltage is reduced under the constant V th, the critical path delay will not meet the timing constraints [6]. As CMOS technologies are scaled, the power supply voltage is lowered. With the general scaling theory, the current I is increasing and the power supply voltage is decreasing. The impedance of the power distribution system should, therefore, be decreased to satisfy to satisfy power noise constraints. The target impedance of a power distribution system is falling at an alarming rate, a factor of five per computer generation.
Recently, a model of the impedance of a power distribution system with two supply voltages was studied [1,3]. Impedance model of the power distribution system with two supply voltages is shown in the Fig. 1. The impedance of the network can be calculated as Upon calculations the impedance of the network turns out to be where Fig. 2. Impedance of power distribution system with two supply voltages and the decoupling capacitors represented as series RLC networks. Fig. 3. Frequency dep
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