GUIDE: GenAI Units In Digital Design Education

GUIDE: GenAI Units In Digital Design Education W eihua Xiao ∗ , Jason Blocklov e ∗ , Matthew DeLorenzo § , Johann Knechtel † , Ozgur Sinanoglu † , Kanad Basu ‡ , Jeya vijayan Rajendran § , Siddharth Garg ∗ , Ramesh Karri ∗ ∗ NYU T andon, USA † NYU Abu Dhabi, U AE ‡ RPI, USA § T exas A&M, USA { wx2356, jmb9986 } @nyu.edu, matthe wdelorenzo@tamu.edu, { johann, ozgursin } @nyu.edu, basuk@rpi.edu, jv .rajendran@tamu.edu, siddharth.j.garg@gmail.com, rkarri@nyu.edu Abstract — GenAI Units In Digital Design Education ( GUIDE ) is an open courseware repository with runnable Google Colab labs and other materials. W e describe the repository’ s architectur e and educational appr oach based on standardized teaching units comprising slides, short videos, runnable labs, and r elated papers. This organization enables consistency f or both the students’ learning experience and the reuse and grading by instructors. W e demonstrate GUIDE in practice with three representati ve units: V eriThoughts f or reasoning and formal-verification-back ed R TL generation, enhanced LLM-aided testbench generation, and LLMPirate for IP Piracy . W e also provide details for four example course instances ( GUIDE4ChipDesign , Build your ASIC , GUIDE4HardwareSecurity , and Hardware Design ) that assemble GUIDE units into full semester offerings, learning outcomes, and capstone projects, all based on pro ven materials. For example, the GUIDE4HardwareSecurity course includes a project on LLM-aided hardware T r ojan insertion that has been successfully deployed in the classroom and in Cyberse- curity Games and Conference ( CSA W ), a student competition and academic conference for cybersecurity. W e also organized an NYU Cognichip Hackathon, engaging students across 24 international teams in AI-assisted R TL design workflows. The GUIDE repository is open for contributions and available at: https://github .com/FCHXWH823/LLM4ChipDesign. Index T erms —LLM, digital design education, RTL, hardware verification, hardware security , open-source courseware I . I N T R O D U C T I O N Lar ge Language Model s ( LLM s) [1] increasingly assist with key steps in digital design and verification [2], including generating Re gister-T ransfer Level ( RTL ) code from informal specifications [3], producing testbenches for simulation [4], and translating design properties into SystemV erilog Assertion s ( SV A s) for property checking [5]. This capability can lo wer the barrier to entry and accelerate iteration, making it attractive for education and training. Digital design comes with strict rules that make “looks correct” outputs risky . R TL must follow pre- cise interfaces, clock/reset behavior , and synthesis constraints, and ev en small issues can lead to incorrect hardw are. For instance, a missing default assignment, an unintended width truncation, or a reset mismatch can cause subtle bugs. T eaching GenAI-driv en digital design raises practical chal- lenges beyond traditional courses. First, the need for rapid tool ev olution: models and prompting workflo ws change quickly . Course materials can be outdated within months. Second, the need to accommodate div erse student backgrounds from different levels and majors (e.g., undergraduate vs. graduate; EE/CE/CS). They have different experiences with hardware description languages (HDLs) and v erification. Hence, one syllabus may not fit everyone. Third, the need for use of Fig. 1. Educational approach for generative AI in chip design using the open- source GUIDE framework. Figure was generated using NotebookLM. complex tools: LLM-aided digital design is not a standalone step but an end-to-end workflo w . This workflo w must be integrated with ED A tools for compilation, simulation, and verification and this integration needs to be taught. W e introduce GUIDE , GenAI Units In Digital Design Education to teach LLM-aided digital design. The key idea is to make course content reusable and easy to update. W e build a public repository with hands-on Google Colab labs. Each unit is a teaching unit with a clear scope. It comes with slides, a short video, a runnable lab, and re- lated paper . Finally , we present four course instances built from the repository , GUIDE4ChipDesign , Build your ASIC , GUIDE4Har dwar eSecurity , and Hardwar e Design , and sum- marize how we selected and organized units into a semester offering, including a syllabus and a capstone. In Section II, we outline the GUIDE architecture and summarize the main topic coverage in our repository . Fur- thermore, we define what a unit is and provide a standard unit architecture, including required teaching materials, and quality requirements. In Section III, we present three sample units to show what a teaching-ready unit looks like in practice. In Section IV, we report four example courses b uilt from GUIDE. In Section V, we discuss future directions. I I . G U I D E A R C H I T E C T U R E GUIDE (see Fig. 1) provides an educational approach and an open-source courseware repository for instructors to teach GenAI topics in digital design in a structured and reusable way . The goal is to turn research results into material that can be used in classes. The material should be easy to adopt, easy to update, and suitable for students with dif ferent backgrounds. GUIDE has a modular structure (T able I) or ganized into top- ics, subtopics, and units. Its three topics are: LLM-aided RTL generation (subtopics: generation from natural language ( NL ), finetuned LLMs), LLM-aided RTL verification (subtopics: simulation-based and formal verification), and LLM-aided har dwar e security (subtopics: attacks and defenses). A unit is the smallest teaching-ready element, corresponding to one concrete teaching objectiv e. A. Standard Unit Structur e GUIDE uses a uniform unit structure so instructors can teach with low setup cost and students can use it easily . Each unit is simple and “teaching-ready” and has four elements: • Slides present the core idea of the unit. They should introduce the problem, define the inputs/outputs, and explain the key concepts that students need. Slides should highlight common pitfalls and include an example. • Short video provides a quick overvie w for self-study and revie w . It should explain what the unit does, the workflow , and what results students should expect. • Colabs provide a hands-on workflo w to run end-to-end (setup, run, check). It includes at least one runnable e xample so students can ex ecute the main steps and see the expected artifacts. If Google Colab is not applicable (e.g., special tools, licensing limits, or heavy compute), the unit should provide a runnable script and clear instructions. • Related papers connect the unit to research context and deeper reading. This helps instructors justify the unit and motiv ates students to explore beyond the lab . B. Quality Requirements for T eaching and Reuse A unit should be “teaching-ready” and easy to reuse across different courses. W e use the following requirements. • Runnable from scratch : The lab should run in a clean en vironment. It should not depend on priv ate paths or local files. If extra packages are needed, the lab should install them or list them clearly . • End-to-end runnable example : Each unit should include at least one runnable example that students can ex ecute end-to- end. The example should make the workflow concrete and show the expected artifacts. • Evidence for grading : The unit should specify what stu- dents must submit as evidence, such as compilation/ simu- lation logs, waveform screenshots, or reports. This reduces the risk of solutions that “look correct. ” • Stable interfaces and file layout : If a unit generates R TL, testbenches, or assertions, it should follow a consistent file naming and folder layout. This makes it easier to combine units into a course project. • Clear explanations : Slides and labs should use simple language. Advanced terms should be defined. I I I . R E P R E S E N TA T I V E U N I T S This section describes representative units in the GUIDE repository . Each example follo ws a consistent format. W e summarize the learning goal, key student outputs, and the re- quired checks. These e xamples sho w ho w the repository cov ers multiple topics in GenAI-driv en digital design education. A. V eriThoughts: Reasoning and F ormal V erification 1) Goal: This unit teaches students to understand how verification-backed reasoning datasets are constructed and to analyze R TL generation quality through the lens of formal equiv alence checking. Students learn why NL prompts alone can be noisy , and ho w a formal-equiv alence-checked synthesis pipeline produces more reliable training data. The unit con- nects course topics (prompting, R TL generation, and formal verification) through a hands-on end-to-end example. 2) W orkflow: Students first select a subset of ground-truth V erilog modules from the V eriThoughts dataset. They then run the V eriThoughts synthesis pipeline on this subset: an LLM generates an NL question for each module, a reasoning- capable LLM produces a step-by-step reasoning trace and a candidate V erilog solution, and a formal equiv alence checker compares each candidate against the ground-truth design and labels it as match or mismatch. Students then analyze the synthesis results — for example, examining how reasoning trace length, prompt style, or module complexity correlates with formal equiv alence outcomes. 3) Outputs and Submission: Students submit: (i) the se- lected subset configuration (which modules, what filtering criteria), (ii) the synthesized dataset including generated NL questions, reasoning traces, candidate V erilog solutions, and formal equiv alence labels, (iii) a formal equiv alence checker log for at least one match and one mismatch example, and (iv) a short analysis report discussing how pipeline or subset choices affect the match/mismatch distribution. B. Enhanced LLM-Aided T estbench Generation 1) Goal: This unit teaches students how to build an end- to-end testbench generation workflo w that produces a self- checking simulation result. The key idea is to pair LLM- generated test patterns with an independent “golden” reference model so the final testbench can automatically report pass/fail. 2) W orkflow: The lab follows a 5-step pipeline: (1–2) take the NL description and the V erilog design-under-test as inputs, (3) use an LLM to generate test patterns and a testbench skeleton, (4) generate a Python golden model from the NL description and compute expected outputs, and (5) enhance the testbench with expected outputs and self-checking logic. 3) Outputs and Submission: Students include a testbench with test patterns, a Python golden reference implementation, a pattern file with expected outputs, and a final self-checking testbench that compares outputs against golden outputs and reports pass/fail. Students also include artifacts and a simula- tion log showing compilation and the final pass/fail summary produced by a standard R TL simulation flow . This is easy to grade while reflecting whether the workflow runs end-to-end. C. LLMPirate: LLMs for IP Piracy 1) Goal: LLMPirate teaches students how LLMs can be maliciously leveraged to obfuscate a circuit design to ev ade T ABLE I G U I D E TA X O N OM Y I N O U R C U R RE N T R E P O SI T O RY : T O P I C S , S U B TO P I C S , A N D R E PR E S E N TA TI V E U N I TS A N D D E S C R I P TI O N S . T opic Subtopic Unit Description LLM-aided R TL Generation R TL Generation from NL AutoChip [6] Generate V erilog from a prompt and testbench plus iterativ e compilation/ simula- tion feedback. R OME [7] Uses hierarchical prompting to decompose comple x designs so smaller open-source LLMs can generate larger V erilog systems with better quality and lower cost. V eritas [8] Has an LLM generate CNF clauses as a formal functional specification and deterministically con v erts CNF to V erilog for correctness by construction. PrefixLLM [9] Represents prefix-adder synthesis as structured text (SPCR) and performs iterativ e LLM-guided design space exploration to optimize area and delay . V eriDispatcher [10] Dispatch R TL tasks to LLMs using pre-inference dif ficulty prediction to improve quality and reduce LLM use cost. Finetuned LLMs for R TL Generation VGen [11] Proposes a dedicated dataset and demonstrates that finetuning LLMs on this dataset significantly improv es their V erilog code generation capabilities. V eriThoughts [12] Provides a formal-verification-based pipeline to build a reasoning-oriented V erilog dataset and to finetune LLMs for high-accuracy V erilog generation. V eriReason [13] A DeepSeek-R1-inspired R TL generation framework that combines supervised finetuning with GRPO reinforcement learning and feedback-driven rewards. V eriContaminated [14] Analyzes data contamination in V erilog benchmarks (V erilogEval, R TLLM) to assess the validity and fairness of SOT A LLM code generation e valuations. LLM Architecture Insights [15] Inspects LLM internals (layers, attention, context) and visualizes parameter shifts during finetuning to understand suitability for hardware constraints. LLM-aided R TL V erification Simulation-based V erification T estbench Generation [4] Giv en the R TL under test and an NL description of the golden R TL, it generates comprehensiv e test patterns and then refines them using feedback from EDA tools to improv e coverage and expose bugs. Enhanced T estbench Generation Starting from the R TL and its description, generate a testbench, build a Python golden model to compute outputs, insert self-checking logic, and run simulation. Formal V erification RA G-based SV A Generation Builds a knowledge base from OpenTitan documentation and uses retrieval- augmented generation to produce context-a ware SV As for IP blocks. SV Assertions [16] Utilizing LLMs to generate SystemV erilog assertions from design documentation. Assert-O [17] Optimization of SystemV erilog assertions using LLMs. Hybrid-NL2SV A [5] A RAG framework for NL2SV A and a finetuning pipeline with a synthetic dataset to train lightweight LLMs to translate NL properties into SV As. LLM-aided Hardwar e Security Hardware Attacks LLMPirate [18] LLM-driv en re writing to thwart piracy-detection tools. A TTRITION [19] An RL framew ork that models an adversary to evaluate and ev ade prior Trojan detectors, sho wing dramatically higher attack success than random insertion. GHOST [20] An automated LLM-based attack framework that generates and inserts stealthy , synthesizable Hardware T rojans into HDL designs, enabling rapid T rojan creation and highlighting detection risks in modern hardware security flows. R TL-Break er [21] A framework assessing backdoor attacks on LLM-based HDL generation, analyz- ing trigger mechanisms and their impact on code quality and security . Hardware Defenses Security Assertions [22] LLM-generated security assertions from NL prompts/comments. NOODLE [23] A multimodal, risk-aware Trojan detection unit that addresses limited T rojan benchmarks by using GAN-based data augmentation and a multimodal deep learning detector with uncertainty estimates for decision making. NSPG [24] Security property generator based on natural-language processing (NLP). T rojanLoC [25] Use R TL-finetuned LLM embeddings plus lightweight classifiers to detect Trojans, predict types, and localize suspicious lines using T rojanInS dataset. LockFor ge [26] A multi-agent LLM framework that automates the translation of logic locking schemes from research papers into executable, v alidated code. SALAD [27] An assessment frame work using machine unlearning to remove sensitive IP , con- taminated benchmarks, and malicious patterns from LLMs without full retraining. piracy detection tools while maintaining functionality . Stu- dents will learn the initial limitations of LLMs in rewriting large-scale V erilog code, and dev elop a prompting framew ork to ov ercome context-windo w and training challenges to suc- cessfully pirate circuit designs from an attacker’ s perspecti ve. 2) W orkflow: This lab consists of dev eloping an iterati ve prompting framework for hardware IP piracy . The assignment begins with students directly prompting an LLM to rewrite a set of V erilog circuits such that the gate-le vel structure is different, while maintaining functionality . Then, the generated circuits will be e v aluated for functional equi v alence and struc- tural similarity to their original counterparts through formal- equiv alence and piracy-detection tools. Students will utilize a Boolean representation of the circuit netlists within the prompt, instructing the model to perform gate-le vel transformations. Then, students will enhance the framew ork through defining iterativ e feedback prompts that utilize the output of the pro- vided tools. The circuits will be ev aluated for functionality and piracy ev asion after each implementation. 3) Outputs and Submission: Students will provide (i) their final prompting frame work consisting of the initial prompt and all tool-feedback prompts, (ii) the functional equiv alence and structural similarity scores for all tested V erilog circuits, and (iii) an ev aluation of scores after each framework implementa- tion, assessing which configuration best facilitated IP piracy . I V . E X A M P L E S F O R G U I D E - D R I V E N C O U R S E S GUIDE is not tied to a single syllabus. Instead, instructors can select GUIDE units and organize them into course in- stances that match their audience, timeline, and learning goals. W e present four examples next. A. Example Course 1: GUIDE4ChipDesign I & II 1) GUIDE4ChipDesign I: This part targets students who already know basic digital design and V erilog. The course focuses on ho w to use LLMs in digital-design workflows, including R TL generation, simulation- and assertion-based verification. The course had 27 students enrolled. GUIDE Units: GUIDE4ChipDesign I selects units span- ning three GUIDE topics: LLM-aided (i) R TL generation, (ii) R TL verification, and (iii) hardware security . Semester Plan: See T able II. Early weeks focus on writing clear specifications, debugging R TL codes with tool feedback, and architectural insights for LLM-aided hardware design. Middle weeks focus on testbench generation. Later weeks introduce properties and SV As. Instructors can swap or reorder weeks based on student background and course goals. Capstone Project: The final project is LLM-Based V er - ilog Adder Generation and V erification . This capstone guides students through an end-to-end LLM-aided digital design workflo w using adders as a focused case study . Students select two different adder architectures from a public repository of golden implementations, rev erse engineer each design into a detailed NL description (architecture, hierarchy , and signal behavior), and use an LLM tool (e.g., AutoChip in our GUIDE repository) to regenerate V erilog that follows the description and matches the required interface. Students then compare the regenerated R TL code against the golden reference at a high lev el (e.g., module structure and key signals). Next, students use an enhanced LLM-aided testbench generator to produce self-checking testbenches that validate both primary outputs and selected internal signals, and they run R TL compilation and simulation to report pass/fail evidence. 2) GUIDE4ChipDesign II: This builds on the first semester and transitions to team-based design projects. The course had 13 teams (two students per team) who propose their own projects. T eams apply the LLM-aided design, verifica- tion, and security techniques from GUIDE4ChipDesign I to complete a full implementation including FPGA deployment. The semester follows a milestone-based structure with weekly presentations. Other deli v erables are a final report (design logs, FPGA validation), a GitHub repo, and a demo video. NYU Cognichip Hackathon. W e organized a hands-on activity that exposed 72 students across 24 teams (21 from the US, one from Canada, two from India) to AI-assisted design workflo ws. Students used the Cognichip [28] platform to dev elop R TL solutions, run simulations, and present method- ologies, connecting GenAI tools with chip design practices. B. Example Course 2: Build your ASIC I & II 1) Build your ASIC I: The first part is a digital-design-to- silicon course experience. Students implement R TL designs, verify them with testbenches, and use the Tin yT apeout [29] workflo ws to run simulation and complete an ASIC-style flow . The course had 12 students enrolled. GUIDE Units: This course can incorporate selected GUIDE units, especially those aligned with LLM-aided design and verification. LLM-related lectures/labs can be placed after students learn basic V erilog syntax and testbench concepts. Semester Plan: T able III summarizes a typical week-by- week plan aligned with the course structure. Capstone Project: The task is Design and Implement an 8- bit Adder from a repository or the student’ s own design, using the Tin yT apeout GitHub workflows. Students write additional test cases. Final submission includes a design report and T iny- T apeout workflo w artifacts: documentation, simulation wav e- forms, GDS files, and implementation statistics (area/routing). 2) Build your ASIC II: T eam-based projects emphasizing C-centric high-level synthesis ( HLS ) methodologies are con- ducted. Students work in teams of two and execute projects significantly more comple x than the first part, demonstrat- ing end-to-end design ability from algorithmic specification through FPGA or ASIC implementation. The course had 6 project teams. The course follows a presentation-driv en mile- stone structure with weekly presentations. Final deliverables include: (1) weekly progress presentations, (2) final project report (5–6 pages minimum) covering design methodology , simulation and synthesis results, FPGA/ASIC implementation, and T inyT apeout process discussion, (3) GitHub repository with C source code, generated R TL, testbenches, and imple- mentation files, (4) Y ouT ube video ( ∼ 10 minutes) showing the working functionality and corner cases on an FPGA board. C. Example Course 3: GUIDE4Har dwar eSecurity This course targets students with a basic background in digital design and focuses on using LLMs for hardware security applications, including both attack and defense sce- narios. The course spans 14 weeks and integrates foundational R TL generation concepts with specialized hardware security units. Part of this course will be used at RPI for Spring 2026 by Dr . Basu for his “Hardware Security” course. with 34 students enrolled, comprising undergraduate and graduate students from Electrical, Computer and Systems Engineering and Computer Science departments. Students work in teams (2–4 per team) for the two capstone projects, which constitute 50% of the course grade. GUIDE Units: GUIDE4HardwareSecurity selects units from two GUIDE topics: (i) LLM-aided R TL generation T ABLE II S E M E ST E R P L A N F O R G U I D E 4 C HI P D E S I G N ( W E E K - L E V E L V I E W ) . W eek Theme T ypical Activities 1 Course setup Course ov ervie w; GenAI for digital design; en vironment setup; first R TL-generation warm-up lab . 2 Prompting basics NL specification writing; interface constraints; compile-first mindset. 3 R TL generation I Generate small combinational V erilog modules; fix compile errors; learn common syntax pitfalls. 4 R TL generation II Sequential R TL patterns; clock/reset con ventions; debug reset mismatches. Analyzing fine-tuning dynamics: visualizing parameter shifts in domain-adapted models. 5 Debugging practice Iterativ e refinement using compiler/simulator feedback; style and structure checks. 6 T estbenches I Self-checking testbenches; directed tests; pass/fail reporting. 7 T estbenches II Corner cases and boundary v alues; debugging using wa veforms and logs. 8 Enhanced v alidation Stronger test patterns; add a simple reference model when possible; evidence-based submissions. 9 Properties I What properties mean; mapping intent to SV As; basic temporal operators. 10 Properties II Common SV A pitfalls; vacuity; disable conditions; re view and correction using examples. 11 NL2SV A practice T ranslate design properties into SV As; compile checks; small-scale trace reasoning when needed. 12 Security aw areness Security mindset for R TL; audit thinking; suspicious patterns to look for. 13 Project integration Integrate R TL + testbench + checks; project milestone revie w and debugging clinic. 14 Capstone wrap-up Final integration, results packaging, and presentation of e vidence (logs/outputs). T ABLE III S E M E ST E R P L A N F O R B U I L D YO U R A S I C ( W E E K - L E V E L V I E W ) . W eek Theme T ypical Activities 1 Introduction Course ov ervie w; setup; expectations and tooling. 2 Combinational logic + testbench Basic modeling; testbench structure; initial lab work. 3 Combinational logic + testbench Continue W eek 2; submit W eek 2 work. 4 Sequential logic modeling 1 + testbench Sequential basics; submit W eek 3 work. 5 Sequential logic modeling 2 + testbench Submit W eek 4 work; preliminary project proposal. 6 LLM-aided chip design 1 Use LLMs to design combinational/sequential logic and testbench; submit W eek 5 work. 7 LLM-aided chip design 2 Continue LLM-aided workflow; finalize project plan. 8 Project simulation (combinational) Run simulation for the combinational part of the project. 9 Project simulation (sequential) Simulate sequential part; submit to TinyT apeout. 10 T inyT apeout submission Submit final project to T inyT apeout workflo w . 11 Documentation + presentations Present progress; prepare chip tapeout documentation. 12 Project report Draft the project report and collect workflow artifacts. 13 Final report submission Submit final report and required artifacts. 14 Course wrap-up Final presentations, feedback, and course review . (W eeks 1-4) and (ii) LLM-aided hardware security (W eeks 5-14), cov ering both attack and defense perspectiv es. Semester Plan: See T able IV. The first four weeks establish foundational skills in R TL generation and LLM-aided design workflo ws. W eeks 5-14 focus exclusi v ely on hardware security applications, alternating between attack-oriented and defense- oriented units to provide comprehensive security awareness. Capstone: T eams insert stealthy T rojans using LLM-based workflo ws (e.g., GHOST [20]) that pass regression tests but trigger under specific conditions, apply defenses (e.g., T rojan- LoC [25]), and ev aluate attack–defense ef fectiv eness. Deliv- erables are modified R TL, detection reports, LLM interaction logs, and simulation evidence. The project has been used in class and at CSA W 2025 [30]. D. Example Course 4: Har dwar e Design at NYU-AD) This course targets students with basic digital-logic knowl- edge and trains them to design advanced V erilog circuits using both manual and LLM-driv en approaches for efficiency com- parison. The 14-week structure uses the first 7 weeks for core combinational/sequential design concepts and AI-vs-manual implementation practice. The last 7 weeks co ver advanced GenAI workflows (datasets, benchmarking, R TL generation, simulation, and verification), culminating in a processor and neural-accelerator class project. The Spring 2026 class has 10 computer-engineering students, and enrollment is expected to grow with semiconductor initiativ es in GCC/MEN A region. GUIDE Units: W e select units from the first two topics of GUIDE, i.e., LLM-aided R TL generation, and verification. Semester Plan: See T able V. W eeks 1–7 cover sequential- design concepts, structural/R TL/beha vioral V erilog coding, and simulation/debugging, with labs (e.g., counters, adders, traffic-light controller) implemented both manually and with LLM tools (e.g., ChatGPT , Gemini). W eeks 8–14 focus on GUIDE units for LLM-aided R TL generation (e.g., AutoChip, R OME, V eritas, VGen, V eriContaminated) and verification techniques such as testbench generation and Hybrid-NL2SV A. Class/Capstone Project: The final project is LLM-Based V erilog Neural Accelerator Generation and V erification . Stu- dents complete an end-to-end LLM-aided workflow us- ing adders, multipliers, MA C units, and interconnects to build a systolic-array-like design. They generate MA C v ari- T ABLE IV S E M E ST E R P L A N F O R G U I D E 4 H AR D W AR E S E C U R I TY ( W E E K - LE V E L V I E W ) . W eek Theme T ypical Activities 1 Course setup Course ov ervie w; GenAI for digital design; en vironment setup; first R TL-generation warm-up lab . 2 Prompting basics NL specification writing; interface constraints; compile-first mindset. 3 R TL generation I Generate small combinational V erilog modules; fix compile errors; learn common syntax pitfalls. 4 R TL generation II Sequential R TL patterns; clock/reset conv entions; debug reset mismatches. Analyzing fine-tuning dynamics: visualizing parameter shifts in domain-adapted models. 5 Security foundations Introduction to hardware security threats; Trojan taxonomy; attack surfaces in digital design. 6 LLM-aided attacks I LLMPirate: LLM-driv en IP piracy and obfuscation techniques; ev ading detection tools. 7 LLM-aided attacks II GHOST : Automated Trojan insertion frame work; generating stealthy , synthesizable Trojans. 8 Advanced attacks A TTRITION: RL-based adversarial framework for hardware designs. 9 Defense foundations Security assertions and property checking; translating security requirements to verifiable properties. 10 LLM-aided defenses I Security Assertions: generating security properties from NL prompts; v alidation. 11 LLM-aided defenses II T rojanLoC: Trojan detection and localization using LLM embeddings; TrojanInS dataset exploration. 12 Advanced defenses NOODLE: multimodal Trojan detection; LockForge: automated logic locking implementation. 13 Attack-defense integration SALAD: machine unlearning for sensiti ve IP protection; integrated attack-defense workflo ws. 14 Capstone presentations T eam presentations of inte grated Trojan insertion-detection projects; peer ev aluation and discussion. T ABLE V S E M E ST E R P L A N F O R H A R DWAR E D E S I GN ( W E E K - LE V E L V I EW ) . W eek Theme T ypical Activities 1 Introduction Overvie w , tool setup, and first V erilog R TL lab. 2 Combinational blocks + testbench Encoders/decoders, mux design, and ALU testbench lab. 3 Sequential logic elements Flip-flops/latches with traffic-light controller lab. 4 Sequential circuit modeling+analysis FSM/state-table modeling and traffic-light verification lab. 5 Sequential circuit design 1 Spec-to-circuit design with counter and pattern-detector labs. 6 Sequential circuit design 2 Registers, hierarchical V erilog, and CPU design lab . 7 Sequential circuit design 3 Counters, PLAs, memory hierarchy , and CPU testbench lab. 8 LLM-aided chip design 1 LLM-based R TL generation and adv anced CPU coding lab . 9 LLM-aided chip design 2 LLM R TL generation for neural-accelerator modules and tests. 10 LLM-aided R TL verification 1 LLM-assisted testbench generation for neural-accelerator blocks. 11 LLM-aided R TL verification 2 Enhanced validation and RA G-based SV A generation lab . 12 Project: LLM-aided core generation and validation 1 MA C-unit generation, validation, and simulation milestone. 13 Project: LLM-aided core generation and validation 2 MA C-array design/v alidation and integrated simulation milestone. 14 Project presentation and course wrapup Final report, presentations, feedback, and course wrap-up. ants with GUIDE/commercial LLM tools, then e v aluate area/performance after v alidation and v erification using an enhanced LLM-aided testbench generator . Final submissions include a report, prompts, R TL, testbenches, and results, which can also be contributed back to GUIDE repositories. V . D I S C U S S I O N A N D F U T U R E D I R E C T I O N S GUIDE provides modular , reusable coursew are for GenAI- driv en digital design education, deriv ed from tutorials [31] at D A TE 2024 , ETS 2024 , and ESWEEK 2024 . This open-source GitHub repository supports di verse course configurations. One colleague who participated in the first offering suggested introductory Colabs for standard tools (Y osys/Icarus) before tackling GenAI tasks, and using peer ev aluation to improve report reproducibility . Such suggestions strengthen the peda- gogical scaffolding, by ensuring students revisit ED A concepts and enabling rigorous reporting alongside GenAI workflows. W e welcome contributions across all GenAI-dri ven design topics and encourage sharing of course modules and teach- ing materials. W ith GUIDE becoming a community-dri ven resource, we aim to create a living repository that benefits educators and students worldwide. The repository focuses on digital design. W e plan to broaden cov erage to: (a) GUIDE4HLS , studying how algo- rithms are translated into synthesizable C/C++ HLS code; (b) GUIDE4PhysicalDesign , LLM-aided open-source placement and routing flows; (c) GUIDE4AnalogCir cuitDesign , LLM- aided SPICE netlist generation. V I . A C K N O W L E D G M E N T S The authors acknowledge the support from the Center for Secure Microelectronics Ecosystem (CSME) #210205, NYU Center for Cybersecurity (CCS) (NYU) and CCS-NYU AD, and National Science Foundation (NSF) #2537759, #2347233 (NYU). Blocklove is funded in part by GAANN Fellowship. Prof. Muhammad Shafique is offering some of these modules at NYU-AD in Spring 2026 (see section IV .D). R E F E R E N C E S [1] A. V aswani, N. Shazeer , N. Parmar , J. Uszkoreit, L. Jones, A. N. Gomez, L. Kaiser , and I. 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