A 1.6-fJ/Spike Subthreshold Analog Spiking Neuron in 28 nm CMOS

The computational complexity of deep learning algorithms has given rise to significant speed and memory challenges for the execution hardware. In energy-limited portable devices, highly efficient processing platforms are indispensable for reproducing the prowess afforded by much bulkier processing platforms. In this work, we present a low-power Leaky Integrate-and-Fire (LIF) neuron design fabricated in TSMC’s 28 nm CMOS technology as proof of concept to build an energy-efficient mixed-signal Neuromorphic System-on-Chip (NeuroSoC). The fabricated neuron consumes 1.61 fJ/spike and occupies an active area of 34 $μm^{2}$, leading to a maximum spiking frequency of 300 kHz at 250 mV power supply. These performances are used in a software model to emulate the dynamics of a Spiking Neural Network (SNN). Employing supervised backpropagation and a surrogate gradient technique, the resulting accuracy on the MNIST dataset, using 4-bit post-training quantization stands at 82.5%. The approach underscores the potential of such ASIC implementation of quantized SNNs to deliver high-performance, energy-efficient solutions to various embedded machine-learning applications.

💡 Research Summary

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The paper presents a novel analog Leaky‑Integrate‑and‑Fire (LIF) neuron fabricated in TSMC’s 28 nm CMOS technology, targeting ultra‑low‑energy neuromorphic processors for edge AI and implantable devices. The authors motivate the work by reviewing prior digital neuromorphic chips (TrueNorth, Loihi) and earlier analog LIF implementations in larger nodes, highlighting the trade‑off between energy per spike, silicon area, and supply voltage. While sub‑threshold operation in 65 nm and 55 nm nodes has already demonstrated femtojoule‑scale spikes, those designs either consume more area or require higher supply voltages, limiting scalability.

The circuit architecture consists of three main blocks: (1) an integration block formed by a current‑mirror (M1–M2) charging a membrane capacitor C_mem, (2) a spike‑generation block realized with a back‑to‑back inverter pair (M5–M8) that fires when the membrane voltage V_mem reaches a sub‑threshold threshold V_th, and (3) a reset block (M3–M4 with C_res) that discharges C_mem after a spike and restores V_mem to V_reset. Leakage is implicitly provided by the sub‑threshold operation of M3 and M4, eliminating the need for a dedicated leak resistor. By carefully sizing the transistors and biasing at a 250 mV supply, the authors achieve a measured energy consumption of 1.61 fJ per spike, a silicon footprint of 34 µm², and a maximum spiking frequency of 300 kHz. Twenty ASIC samples were tested, showing consistent performance (average 1.64 fJ/spike, 33.8 µm² area) and robustness against process‑voltage‑temperature (PVT) variations.

To validate the circuit beyond silicon, the authors develop a parameterized software model that reproduces the measured f‑I curves. This model is then employed to train a spiking neural network (SNN) on the MNIST handwritten‑digit benchmark. Using surrogate‑gradient back‑propagation and 4‑bit post‑training quantization, the network reaches 82.5 % classification accuracy. The energy per inference is estimated at roughly 1 pJ, which is an order of magnitude lower than typical digital SNN implementations, albeit with a modest accuracy penalty.

The discussion acknowledges several limitations: the current neuron implements only the basic LIF dynamics without adaptive mechanisms (e.g., spike‑frequency adaptation, refractory‑period modulation), and the system lacks on‑chip learning circuitry. Integration with non‑volatile memory synapses (RRAM, PCM) and the addition of local learning rules such as STDP or gradient‑based updates are identified as future work. Moreover, scaling to even smaller nodes (<28 nm) will require careful compensation for increased sub‑threshold current variability.

In conclusion, the work demonstrates that a 28 nm analog LIF neuron can simultaneously achieve sub‑femtojoule energy per spike, sub‑50 µm² area, and sub‑300 mV operation, establishing a compelling building block for high‑density, ultra‑low‑power neuromorphic System‑on‑Chips. The combined silicon measurements and system‑level SNN validation illustrate the feasibility of deploying such neurons in energy‑constrained edge AI applications, biomedical implants, and other domains where power and area budgets are paramount.