Modular memristor model with synaptic-like plasticity and volatile memory

Compact models of memristors are essential for simulating large-scale neuromorphic systems, yet they often do not include description of complex dynamics like volatile relaxation and synaptic plasticity. We introduce a modular, computationally efficient memristor model that bridges this gap by integrating principles from physics and computational neuroscience. The model defines a framework consisting of a standard formulation of memristive device dynamics, a functional rule mapping state variables to cumulative conductance, a volatility module inspired by the theory of linear viscoelasticity and a saturation module implementing a linear-nonlinear technique. Additionally, we develop a formulation of synaptic-like plasticity inspired by a biological spike-timing-dependent plasticity (STDP) rule, which is compatible with the general framework for memristive devices. Finally, we propose a Laplace transform-based technique to derive the precise form of the mapping from state variables to cumulative conductance, replacing ad hoc voltage-current relationships with principled construction. We quantitatively validate the complete model against a rich set of experimental data from polymeric memristors exhibiting potentiation, synaptic-like plasticity and volatile decay. Our work presents a new paradigm for memristor modeling that is both practical for large-scale simulation and rich in explanatory power, providing a principled tool for the design of next-generation neuromorphic hardware.

💡 Research Summary

The paper addresses a critical gap in compact memristor modeling for neuromorphic computing: existing models such as TEAM, VTEAM, and V‑VTEAM capture either non‑volatile switching or volatile relaxation, but they rarely combine both volatile dynamics and synaptic‑like plasticity in a single, computationally tractable framework. To fill this void, the authors propose a modular, voltage‑driven memristor model that integrates four essential functional blocks—(1) a core switching dynamics module based on established voltage‑controlled memristor equations, (2) a biologically inspired spike‑timing‑dependent plasticity (STDP) module reformulated for continuous voltage signals, (3) a cumulative conductance function H(s,w) that maps internal state variables to a non‑volatile conductance, and (4) a volatility module derived from linear viscoelasticity theory, which convolves the differential of H with a hereditary kernel kₑᵣ(t). A final saturation block implements a linear‑nonlinear (LN) transformation to keep the resulting conductance within physical bounds.

The model introduces four internal state variables: s (the traditional memristive state), w (a synaptic weight), and x, y (presynaptic and postsynaptic eligibility traces). The voltage‑controlled dynamics for s can be as simple as a linear relation (ṡ = μv) or a piecewise nonlinear function that captures thresholded switching. The STDP block replaces discrete spike trains with the positive and negative components of the applied voltage (v₊, v₋). Traces x and y obey exponential decay with time constants τ₊ and τ₋ and are driven by v₊ and v₋, respectively. The weight w evolves according to
 ẇ = x A₊(w) v₋ – y A₋(w) v₊,
mirroring the causal and anti‑causal updates of biological synapses while remaining bounded only by the later saturation stage.

The cumulative conductance H(s,w) is defined through a differential relation dH = ∂ₛH · ṡ + ∂_wH · ẇ, which can be linear (h₁ṡ + h₀ẇ) or include nonlinear absolute‑value terms (e.g., (h₁₁|s|ᵅ + h₁₀)ṡ). Volatility is introduced by convolving dH with a kernel kₑᵣ(t). The authors discuss two families of kernels: exponential (kₑᵣ(t)=e^{‑a t}) and power‑law (kₑᵣ(t)=1/(t+ε)ᵅ). The power‑law kernel, decaying roughly as 1/t, captures a broad distribution of relaxation times typical of disordered polymeric systems and percolation‑driven conduction pathways. The volatile cumulative conductance is then H_vol = kₑᵣ ∗ dH, where “∗” denotes a Stieltjes convolution over time.

Because the raw H_vol can exceed realistic conductance limits or become negative, a saturation function sat(·) is applied: G = sat(H_vol). This LN block can be a simple clipping, a sigmoid, or any monotonic mapping that enforces physical bounds while preserving differentiability for circuit simulators.

A notable methodological contribution is the use of Laplace transforms to extract the explicit forms of both the kernel kₑᵣ(t) and the cumulative conductance H(s,w) directly from experimental pulse‑response data. By fitting the Laplace‑domain representation of measured current‑voltage transients to the model’s transfer function, the authors obtain device‑specific parameters without resorting to ad‑hoc fitting.

The model is validated against a polymeric memristor consisting of a thin film of poly(N‑(3‑(9H‑carbazol‑9‑yl)propyl)methacrylamide) sandwiched between ITO and a top metal electrode. Experimental observations include: (i) bistable high‑voltage switching with an ON/OFF ratio ≈200, (ii) analog conductance modulation under low‑amplitude pulse trains resembling potentiation and depression, (iii) volatile decay of conductance after stimulus cessation, and (iv) STDP‑like weight updates when paired positive/negative voltage pulses are applied with varying inter‑pulse intervals. Using the Laplace‑derived parameters, the simulated I‑V hysteresis, decay curves, and STDP windows match the measured data quantitatively, confirming the model’s predictive capability.

From a systems perspective, the modular architecture allows independent selection or replacement of any block: different voltage‑controlled core equations, alternative kernels (e.g., stretched exponentials), or more sophisticated saturation functions can be swapped without altering the overall formulation. This flexibility makes the model applicable across a wide range of memristive technologies (oxide‑based, ferroelectric, organic) and operating regimes (voltage‑driven, current‑driven). Moreover, the model’s differential‑equation form is readily implementable in standard circuit simulators (SPICE, Verilog‑A), enabling large‑scale neuromorphic network simulations with realistic device dynamics and learning rules.

In summary, the authors deliver a comprehensive, physics‑grounded, and computationally efficient memristor model that simultaneously captures volatile relaxation, non‑volatile conductance, saturation, and biologically inspired plasticity. By bridging device‑level physics with system‑level learning mechanisms, the work provides a valuable tool for the design, optimization, and verification of next‑generation neuromorphic hardware, potentially accelerating the transition from prototype devices to scalable, low‑power artificial neural systems.