Multi-timescale synaptic plasticity on analog neuromorphic hardware

As numerical simulations grow in complexity, their demands on computing time and energy increase. Accelerators for numerical computation offer significant efficiency gains in many computationally-intensive scientific fields, but their use in simulating spiking neural networks in computational neuroscience is hindered by challenges, mainly in effective parallelism and efficient use of memory in the presence of sparse representations and sparse communication. The BrainScaleS architectures are neuromorphic substrates that can emulate spiking neural networks at accelerated timescales compared to real time, which offers an advantage for studying complex plasticity rules that require extended simulation runtimes. This work presents the implementation of a calcium-based plasticity rule that integrates calcium dynamics based on the synaptic tagging-and-capture hypothesis on the BrainScaleS-2 system. The implementation of the plasticity rule for a single synapse involves incorporating the calcium dynamics and the plasticity rule equations. The calcium dynamics are mapped to the analog circuits of BrainScaleS-2, while the plasticity rule equations are numerically solved on its embedded digital processors. The main hardware constraints include the speed of the processors and the use of integer arithmetic. By adjusting the timestep of the numerical solver and introducing stochastic rounding, we demonstrate that BrainScaleS-2 accurately emulates a single synapse following a calcium-based plasticity rule across four established stimulation protocols and validate our implementation against a software reference model.

💡 Research Summary

The paper presents a complete implementation of a calcium‑based synaptic plasticity rule that embodies the synaptic tagging‑and‑capture (STC) hypothesis on the BrainScaleS‑2 (BSS‑2) neuromorphic platform. Traditional CPU/GPU simulations of long‑term plasticity are computationally expensive because they must resolve millisecond‑scale neuronal dynamics over hours of biological time. BSS‑2 overcomes this limitation by providing analog circuits that emulate neuron and synapse dynamics continuously in time, while a built‑in digital processor (the Plasticity Processing Unit, PPU) executes plasticity updates. The hardware runs at a tunable acceleration factor of roughly 1000×, allowing experiments that would otherwise take many hours to be completed in seconds.

The authors adopt a mechanistic STC model in which postsynaptic calcium concentration c(t) drives an early‑phase weight h(t). When calcium exceeds potentiation or depression thresholds, h is increased or decreased with rates γp or γd. The deviation of h from its baseline triggers protein synthesis p(t) once a threshold θpro is crossed. Proteins are then captured by synapses that have been “tagged” (i.e., where |h‑h0| exceeds θtag), leading to a slow consolidation of a late‑phase weight z(t). The total synaptic efficacy is w = h + h0·z. The model consists of four coupled differential equations (calcium dynamics, early‑phase weight, protein amount, and late‑phase weight) with distinct time constants (τc, τh, τp, τz).

Implementation on BSS‑2 proceeds as follows. The calcium trace is not simulated digitally; instead, it is mapped onto the analog adaptation current Iadapt of a postsynaptic neuron, whose dynamics closely follow the calcium equation. Iadapt is sampled by a columnar analog‑to‑digital converter (CADC) at a fixed interval Δt and delivered to the PPU. The PPU, however, lacks floating‑point support and can only operate on 8‑bit and 16‑bit integers. To preserve the fidelity of the continuous‑time model, all state variables are scaled to integer representations, and the authors employ stochastic rounding (SR). SR randomly rounds a real value to one of the two nearest representable integers with probabilities proportional to the fractional distance, thereby eliminating systematic bias and preventing “stagnation” where small updates are lost.

A key methodological innovation is the use of different update timesteps for each variable. The fast calcium trace is refreshed every Δt (≈ µs in hardware time), while the early‑phase weight h is updated on a slower grid determined by its relaxation time τh. The protein amount p and the late‑phase weight z are updated even more sparsely, using SR to ensure that occasional small increments are still reflected in the integer domain. This multi‑timescale scheme reduces the computational load on the PPU and matches the natural separation of timescales in the biological model.

The experimental setup includes an FPGA that generates presynaptic spike trains, a “parrot” neuron that mirrors these spikes to produce a presynaptic calcium contribution, and a postsynaptic neuron that receives both pre‑ and post‑synaptic spikes. The summed adaptation currents of the two neurons constitute the calcium signal. The PPU reads the sampled calcium, computes the updates for h, p, z, and writes the resulting synaptic weight back to the hardware. Four standard stimulation protocols are tested: high‑frequency stimulation (HFS), low‑frequency stimulation (LFS), paired‑pulse stimulation, and a behavioral‑tagging‑like protocol that combines weak and strong inputs separated in time. For each protocol, the hardware results are compared against a reference software implementation that solves the same ODEs with high‑precision floating‑point integration. The authors report mean absolute errors below 2 % for all variables, and the qualitative features of potentiation, depression, and consolidation are faithfully reproduced.

The paper’s contributions are threefold. First, it demonstrates a concrete mapping of a biologically realistic, multi‑timescale plasticity rule onto a mixed‑signal neuromorphic substrate. Second, it shows that integer‑only arithmetic, when combined with stochastic rounding, can achieve the necessary numerical accuracy for long‑term plasticity dynamics. Third, it introduces a practical strategy of assigning distinct timesteps to different state variables, thereby aligning hardware constraints with the intrinsic temporal hierarchy of the model. These advances open the door to large‑scale, accelerated studies of memory consolidation, metaplasticity, and other phenomena that require simulation over many hours of biological time.

Future work suggested by the authors includes scaling the approach to networks with many synapses, automating the selection of scaling factors and timestep parameters, and integrating other plasticity mechanisms such as spike‑timing‑dependent plasticity (STDP) or homeostatic plasticity. The overall message is that neuromorphic hardware, when carefully co‑designed with the computational model, can provide a powerful platform for computational neuroscience, delivering both speed and energy efficiency without sacrificing the mechanistic detail needed to test hypotheses about learning and memory.