A time-to-digital converter with steady calibration through single-photon detection

Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs present a viable alternative to ASIC ones, once the non-linear behavior due to the intrinsic nature of the device is properly mitigated. To compensate for said nonlinearities, a calibration procedure is required, which should be maintained throughout its runtime. Here we present the design and the demonstration of a TDC that is FPGA-based showing a residual FWHM jitter of 27 ps, that is scalable for multichannel operation. The target application in Quantum Key Distribution (QKD) is discussed with a calibration method based on the exploitation of single-photon detection that does not require stopping the data acquisition or using any estimation methods, thus increasing accuracy and removing data loss. The calibration was tested in a relevant environment, investigating the behavior of the device between 5 °C and 80 °C. Moreover, our design is capable of continuously streaming up to 12 Mevents/s for up to ~1 week without the TDC overflowing making it ready for a real-life scenario deployment.

💡 Research Summary

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This paper presents MARTY, a field‑programmable gate array (FPGA) based time‑to‑digital converter (TDC) designed for quantum communication applications, especially quantum key distribution (QKD). Implemented on a Xilinx Zynq‑7020 System‑on‑Chip, MARTY combines a coarse 48‑bit counter driven by a 412.5 MHz clock with a fine‑resolution tapped delay line (TDL) built from 36 CARRY4 blocks (144 fast‑carry elements). The coarse counter provides a runtime of roughly one week before overflow, while the TDL spans the full 2.42 ns clock period with 130‑135 bins, yielding a nominal resolution of about 19 ps.

Traditional FPGA TDCs rely on static code‑density calibration using a ring oscillator (RO) to generate a uniformly distributed reference signal. This method requires pausing data acquisition for about 30 ms to collect ~131 k events, after which each bin’s propagation time δtᵢ is derived from the histogram counts. Although accurate under stable conditions, the static approach cannot compensate for drift during long‑term operation, especially under temperature variations.

MARTY introduces “steady calibration,” an event‑driven continuous calibration scheme that eliminates acquisition downtime. The method exploits the natural stream of single‑photon detection events already present in a QKD setup. The code‑density histogram is maintained as an ordered FIFO: each new photon event appends a count while the oldest entry is removed, thereby updating bin statistics in real time. Consequently, calibration parameters continuously track environmental changes without interrupting the measurement flow.

The device streams timestamps to a host PC via a double‑buffered block RAM (BRAM) and a CPU‑managed DMA engine over a 1 Gbps Ethernet link. By balancing BRAM fill and transfer times, MARTY achieves a sustained throughput of up to 12 Mevent/s, limited only by Ethernet overhead. A request‑based mode is also provided, allowing the host to pull data at 50 ms intervals without stalling acquisition.

Temperature characterization from 5 °C to 80 °C demonstrates that steady calibration keeps the residual full‑width‑half‑maximum (FWHM) jitter at 27 ps or below, a substantial improvement over conventional FPGA TDCs whose jitter can drift by hundreds of picoseconds across the same range. In a QKD demonstration, MARTY processed a 1 Gbps single‑photon stream, and the continuous calibration yielded a 12 % increase in secret‑key generation rate compared with a state‑of‑the‑art ASIC TDC. The system’s ability to operate continuously for a week without overflow makes it suitable for satellite‑based QKD, where contact windows are short and environmental conditions are harsh.

Compared with alternative calibration strategies—static code‑density, drift‑estimation, and dual‑chain architectures—MARTY offers the following advantages: (1) no acquisition pause, (2) minimal additional logic overhead (no second delay line), (3) exploitation of existing photon sources, and (4) scalability to multiple channels by replacing CARRY4 with newer fast‑carry primitives (e.g., CARRY8 on UltraScale+ devices). Limitations include dependence on sufficient photon flux to keep the histogram statistically uniform; low count rates could slow convergence. Future work will address multi‑channel cross‑calibration, adaptive weighting for non‑uniform photon streams, and migration to newer FPGA families to increase channel count and data rate.

In summary, MARTY demonstrates that a carefully designed FPGA TDC, coupled with an event‑driven steady calibration scheme, can deliver picosecond‑level timing accuracy, robust temperature performance, and uninterrupted high‑throughput operation, fulfilling the stringent requirements of modern quantum communication systems.