Graphene FET Process and Analysis Optimization in 200 mm Pilot Line Environment

The maturity of the chemical vapor deposition graphene-based device processing has increased from chip level demonstrations to wafer-scale fabrication in the past few years. Due to this wafer-scale, electrical characterization and analysis of the fabricated devices has become increasingly important to enable extraction of multiple parameters with minimal number of measurements for the quality control purposes critical for industrial uptake of 2D materials-based devices. As a crucial step, we demonstrate optimization of complementary metal-oxide semiconductor (CMOS) back-end-of-line (BEOL) compatible graphene field-effect transistor (GFET) fabrication and analysis including the gate stack, bottom contact, graphene patterning and encapsulation process steps. The analysis methods include atomic force microscopy, scanning electron microscopy and most importantly electrical characterization. The electrical characterization focuses on comparing different test structures and extraction methods for mobility, contact resistance, IV-curve hysteresis and doping parameters. The comparison shows that the selected measurement test structures and analysis methods can have a large impact on the extracted values and should thus be considered when comparing data sets between different sources. The analysis shows that the optimized process offers high device yield of 98 % with good doping uniformity, contact resistance and mobility as well as low IV-curve hysteresis values on 200 mm wafers.

💡 Research Summary

This paper presents a comprehensive study on the fabrication, optimization, and wafer‑scale electrical characterization of graphene field‑effect transistors (GFETs) that are compatible with CMOS back‑end‑of‑line (BEOL) processing on 200 mm wafers. The authors first develop a modular process flow that includes a local back‑gate, bottom metal contacts, CVD graphene transfer, photolithographic patterning, and encapsulation. Six pilot runs (Runs 1‑6) are used to refine each module: the back‑gate metal is switched from Al/NbN to Ti/Au and the deposition method changed from etching to lift‑off, reducing the gate RMS roughness from 1.9 nm to 0.9 nm and the step height from 77 nm to 33 nm. Bottom contacts (3 nm Ti/30 nm Au) are defined before graphene transfer to minimize post‑transfer processing and residue. Graphene is transferred by a semi‑dry method from Graphenea and patterned by O₂ plasma. Run 7 investigates the impact of one‑ versus two‑layer resist lithography (AZ5214 alone versus PMGI + AZ5214) on resist residue and doping uniformity; the two‑layer approach yields significantly lower residue thickness and tighter Dirac‑point distribution. Encapsulation consists of a 1 nm Al seed layer (oxidized), 50 nm ALD Al₂O₃, and a 100 nm PECVD Si₃N₄ cap, with selective openings for sensor areas.

For metrology, the authors employ AFM and SEM to quantify surface roughness, step heights, edge discontinuities, and residual resist thickness. Electrical testing is performed on a suite of test structures distributed across the wafer: standard GFETs, gated transmission‑line‑model (gTLM) structures, gated cross‑bridge Kelvin (gCBK) resistors, and metal‑insulator‑metal (MIM) / metal‑insulator‑semiconductor (MIS) capacitors. The gTLM structures enable simultaneous extraction of sheet resistance (R_sh) and contact resistance (R_c) by linear fitting of total resistance versus channel length at each gate over‑drive voltage (V_GSO). Gate capacitance per unit area (C_g) is measured on the capacitors, yielding C_g ≈ 1.45 × 10⁻³ F m⁻², which is then used in the Drude mobility expression μ = 1/(e·n·R_sh)·(L/W). Mobility is also obtained from direct transconductance (DTM) and from the simple sheet‑conductance formula, providing cross‑validation. Contact resistance is measured directly with gCBK structures, normalizing by channel width to obtain a specific contact resistance (Ω·µm).

The study demonstrates that the choice of test structure and extraction methodology can shift extracted values by up to 10 %, underscoring the need for standardized protocols when comparing data across laboratories. The optimized process delivers electron and hole mobilities of roughly 2 000 cm² V⁻¹ s⁻¹ at carrier concentrations of ±1 × 10¹² cm⁻², a specific contact resistance below 200 Ω·µm, and a Dirac‑point voltage spread of less than ±0.2 V across the wafer, indicating excellent doping uniformity. IV‑curve hysteresis, quantified as the normalized shift of the Dirac point during forward‑and‑reverse gate sweeps, is reduced to ≤0.05 V, reflecting the effectiveness of the encapsulation and low‑residue patterning.

Yield criteria are defined as on/off current ratio > 5, channel resistance < 1 MΩ, and gate leakage < 10 nA. Under these conditions, the process achieves a 98 % device yield on 200 mm wafers. The authors conclude that the combination of (i) low‑roughness back‑gate and contacts, (ii) residue‑free graphene patterning, (iii) comprehensive test‑structure suite, and (iv) BEOL‑compatible encapsulation provides a robust pathway for large‑scale production of high‑performance GFETs. This work lays the groundwork for industrial‑scale quality‑control protocols essential for the commercialization of graphene‑based sensors (gas, biosensing, infrared imaging) and other 2‑D material electronic systems.