Millisecond-Scale Calibration and Benchmarking of Superconducting Qubits

Superconducting qubit parameters drift on sub-second timescales, motivating calibration and benchmarking techniques that can be executed on millisecond timescales. We demonstrate an on-FPGA workflow that co-locates pulse generation, data acquisition, analysis, and feed-forward, eliminating CPU round trips. Within this workflow, we introduce sparse-sampling and on-FPGA inference tools, including computationally efficient methods for estimation of exponential and sine-like response functions, as well as on-FPGA implementations of Nelder-Mead optimization and golden-section search. These methods enable low-latency primitives for readout calibration, spectroscopy, pulse-amplitude calibration, coherence estimation, and benchmarking. We deploy this toolset to estimate $T_1$ in 10 ms, optimize readout parameters in 100 ms, optimize pulse amplitudes in 1 ms, and perform Clifford randomized gate benchmarking in 107 ms on a flux-tunable superconducting transmon qubit. Running a closed-loop on-FPGA recalibration protocol continuously for 6 hours enables more than 74,000 consecutive recalibrations and yields gate errors that consistently retain better performance than the baseline initial calibration. Correlation analysis shows that recalibration suppresses coupling of gate error to control-parameter drift while preserving a coherence-linked performance. Finally, we quantify uncertainty versus time-to-decision under our sparse sampling approaches and identify optimal parameter regimes for efficient estimation of qubit and pulse parameters.

💡 Research Summary

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The paper addresses the pressing problem that superconducting qubit parameters can drift on sub‑second, even millisecond, timescales, which makes conventional calibration and benchmarking pipelines—typically involving data transfer to a host CPU, offline analysis, and round‑trip updates—far too slow to keep up with the dynamics of the device. To overcome this bottleneck, the authors develop a fully on‑FPGA workflow on the Quantum Machines OPX1000 control system, integrating pulse generation, data acquisition, real‑time analysis, optimization, and feed‑forward into a single hardware loop.

Three technical innovations underpin the workflow. First, they introduce Analytic Decay Estimation (ADE), a closed‑form three‑point estimator for exponential (e.g., T₁, T₂) and sinusoidal response functions. ADE eliminates iterative fitting, is SPAM‑independent, and can be implemented with minimal arithmetic and memory resources, making it ideal for FPGA execution. Second, they implement a generic N‑dimensional Nelder‑Mead optimizer directly on the FPGA, allowing rapid two‑parameter readout optimization (frequency detuning Δf_RO and amplitude A_RO). By evaluating the signal‑to‑noise ratio (SNR) on‑chip, the optimizer converges in about 20 iterations, delivering optimal readout settings in roughly 100 ms—orders of magnitude faster than a dense sweep that would take several seconds. Third, they embed a one‑dimensional golden‑section search (GSS) for peak‑finding in spectroscopy, again avoiding large memory footprints and achieving convergence in a handful of iterations within a few milliseconds.

These primitives are combined into concrete calibration tasks. T₁ tracking uses ADE with three delays chosen adaptively based on the latest estimate; a full T₁ estimate is produced in 9.8 ms, compared to ~250 ms for a conventional dense‑sampling fit. Readout optimization, π‑pulse amplitude calibration, and spectroscopy peak location are all performed in the sub‑100 ms regime. Most notably, Clifford Randomized Benchmarking (CRB) is accelerated by applying ADE to three sequence lengths, reducing the total time‑to‑decision to 107 ms while still extracting a reliable error per Clifford.

A long‑duration experiment demonstrates the practical impact: the authors run a closed‑loop recalibration for six hours, performing more than 74 000 recalibrations. Throughout this period, gate errors remain consistently lower than those obtained from the initial calibration. Correlation analysis shows that the recalibration loop suppresses the coupling between gate error and slowly drifting control parameters (e.g., qubit frequency), while preserving the underlying coherence‑limited performance.

Finally, the authors quantify the trade‑off between the number of sampled points and the resulting estimator variance. By varying the sparsity of the sampling schedule, they identify regimes where a three‑point ADE yields acceptable uncertainty for rapid feedback, and where adding a few more points can improve precision with only modest increases in latency. This systematic analysis provides a practical guide for experimentalists to balance speed and accuracy when designing real‑time calibration loops.

In summary, the work delivers a comprehensive, hardware‑centric solution for millisecond‑scale calibration and benchmarking of superconducting qubits. By co‑locating all stages of the control stack on the FPGA, the authors achieve orders‑of‑magnitude reductions in latency, enable continuous autonomous recalibration, and demonstrate that such fast loops can materially improve gate fidelity in the presence of realistic, fast‑varying environmental noise. The techniques presented are broadly applicable to other quantum hardware platforms where rapid parameter drift is a limiting factor, and they set a clear path toward scalable, high‑fidelity quantum processors that can self‑correct on the timescales dictated by their own physical fluctuations.