Fault Tolerant Design of IGZO-based Binary Search ADCs

Thin-film technologies such as Indium Gallium Zinc Oxide (IGZO) enable Flexible Electronics (FE) for emerging applications in wearable sensing, personal health monitoring, and large-area systems. Analog-to-digital converters (ADCs) serve as critical sensor interfaces in these systems. Yet, their vulnerability to manufacturing defects remains poorly understood despite unipolar technologies’ inherently high defect densities and process variations compared to mature CMOS technologies. We present a hierarchical fault injection framework to characterize defect sensitivity in Binary Search ADCs implemented in n-type only technologies. Our methodology combines transistor-level defect characterization with system-level fault propagation analysis, enabling efficient exploration of both single and multiple fault scenarios across the conversion hierarchy. The framework identifies critical fault-sensitive circuit components and enables selective redundancy strategies targeting only the most sensitive components. The resulting defect-tolerant designs improve fault coverage from 60% to 92% under single-fault injections and from 34% to 77.6% under multi-fault injection, while incurring only 4.2% area overhead and 6% power increase. While validated on IGZO-TFTs, the methodology applies to all emerging unipolar technologies.

💡 Research Summary

The paper addresses the reliability challenge of analog‑to‑digital converters (ADCs) built with flexible‑electronics (FE) technologies, focusing on a binary‑search ADC implemented in n‑type only Indium‑Gallium‑Zinc‑Oxide (IGZO) thin‑film transistors (TFTs). FE devices offer low‑temperature processing, large‑area fabrication, and mechanical compliance, but they suffer from high defect densities, lack of complementary p‑type devices, and pronounced process variations. Conventional CMOS fault models are therefore insufficient for these emerging unipolar technologies.

To quantify defect sensitivity, the authors develop a hierarchical fault‑injection framework that spans transistor‑level defect modeling, subcircuit behavioral abstraction, and system‑level impact assessment. At the transistor level, two fault mechanisms are modeled: opens (high‑impedance 250 MΩ) and shorts (low‑impedance 10 Ω) introduced at gate, drain, or source terminals. These defects are injected into Spectre netlists of the IGZO comparator blocks, and transient simulations generate a fault library that maps each defect location to its functional impact.

The binary‑search ADC’s cascade of decision stages creates a unique fault propagation pattern. A fault in an early stage (e.g., the first comparator, COM0) can misdirect the entire search, leading to catastrophic output errors, whereas faults in later stages tend to be marginal or benign. The framework classifies fault impact based on the resulting Differential Non‑Linearity (DNL) degradation into three categories: Benign, Marginal, and Catastrophic.

Using this sensitivity data, the authors propose selective redundancy strategies aimed only at the most vulnerable components. Two concrete techniques are demonstrated: (1) duplicating the early‑stage comparator to provide a fallback path, and (2) inserting small replica subcircuits at each decision branch to allow alternative routing when a fault is detected. These modifications increase the ADC’s area by only 4.2 % and its static power consumption by 6 %, yet they raise single‑fault coverage from 60 % to 92 % and multi‑fault coverage from 34 % to 77.6 %.

The methodology is validated on a 3‑bit IGZO binary‑search ADC, a representative low‑resolution converter for wearable biomedical and environmental sensing. The authors argue that the approach scales linearly with resolution (N‑bit converters require N comparison stages), and that the critical vulnerability points remain concentrated in the early stages regardless of N. Consequently, the same selective‑redundancy scheme can be applied to higher‑resolution designs with modest overhead.

Beyond IGZO, the paper emphasizes that the hierarchical fault‑injection framework and the targeted redundancy concepts are applicable to any n‑type only emerging technology, such as Indium‑Tin‑Oxide (ITO), Gallium‑Nitride (GaN), and negative‑capacitance FETs (NCFETs). By integrating defect‑sensitivity analysis into the FE design flow, fault resilience can be treated as a first‑class metric alongside performance, power, and area, enabling robust analog and mixed‑signal building blocks for the next generation of flexible, low‑cost electronic systems.