2.5D co-packaged optical I/O chipsets on a SiON/Si interposer for 4 $ imes$ 100G optical interconnection

Optical I/O technologies have emerged as a potential industrial solution for high-performance data interconnection in AI/ML computing acceleration. While optical I/Os are deployed at the edge of computational chips by co-packaged optics (CPO), flexible and high-performance integration architectures need to be explored to address system-level challenges. In this work, we present and experimentally demonstrate a SiON/Si-based optical interposer that integrates high-bandwidth and energy-efficient optical I/O chipsets. High-performance photonic and electronic components are co-packaged on the interposer, leading to low-loss, signal-integrity-friendly, and thermally efficient characteristics. The optical interposer incorporates low-loss SiON photonic circuits to realize scalable waveguide routing and wavelength-division multiplexing (WDM) with polarization-insensitive operation and high fabrication tolerance, while supporting flip-chip integration with InP-based active devices, including electro-absorption modulated lasers (EMLs) and photodetectors (PDs). Based on this architecture, a 400-Gb/s single-fiber optical transceiver is implemented and experimentally evaluated. Clear eye diagrams and high receiver sensitivity demonstrate reliable high-speed data transmission, which offers scalable, high-bandwidth optical I/Os in future high-performance computational clusters.

💡 Research Summary

The paper presents a novel 2.5‑D co‑packaged optical I/O architecture that integrates high‑performance photonic and electronic chiplets on a silicon‑oxynitride (SiON)/silicon (Si) optical interposer, targeting 4 × 100 Gb/s (total 400 Gb/s) short‑reach interconnects for AI/ML accelerators. The authors argue that conventional silicon‑photonic I/O solutions face challenges such as high propagation loss, limited layout flexibility, and thermal constraints, especially when scaling to many channels in a confined chip‑edge area. By leveraging the low‑index‑contrast, low‑loss, and broadband transparency of SiON waveguides, the interposer provides a passive photonic platform that is tolerant to fabrication variations and temperature fluctuations.

Key passive components include coarse‑wavelength‑division‑multiplexing (CWDM) arrayed waveguide gratings (AWGs) for multiplexing and demultiplexing. Measured insertion loss is –2.25 dB per channel for the MUX and –1.25 dB per channel for the DeMUX, with a flat‑top passband of ~13 nm and crosstalk below –20 dB. Central wavelength drift across 240 channels is limited to an average of 1.2 nm (max 3 nm), demonstrating excellent process tolerance. Fiber‑to‑chip couplers exploit the weak confinement of SiON modes to achieve low coupling loss without complex edge‑coupler structures.

Active devices are InP‑based electro‑absorption modulated lasers (EMLs) and photodetectors (PDs) that are flip‑chip bonded onto the interposer. Electronic driver and transimpedance amplifier (TIA) chiplets are also flip‑chip attached, placing them in immediate proximity to the optical devices. This layout minimizes electrical trace length, reduces parasitic inductance and capacitance, and improves signal‑integrity (ESI) at multi‑gigahertz frequencies. The SiON/SiO₂ dielectric stack offers high resistivity and low dielectric loss, further suppressing unwanted coupling. Thermal management benefits from direct metal contacts to the silicon substrate, providing an efficient heat‑spreading path for the densely packed chiplets.

The complete system is evaluated as a single‑fiber transceiver that simultaneously carries four 100 Gb/s channels using CWDM. Eye diagrams show clear openings at 25 Gb/s per lane, and receiver sensitivity reaches –15 dBm, confirming reliable high‑speed data transmission. The demonstrated 400 Gb/s link validates the architecture’s ability to deliver scalable, high‑bandwidth optical I/Os while maintaining low power consumption and a compact footprint suitable for integration next to compute chips.

In summary, the work showcases how a SiON/Si optical interposer can serve as a low‑loss, fabrication‑tolerant passive backbone, while heterogeneous integration of InP active devices and silicon electronic chiplets delivers a high‑performance, thermally efficient co‑packaged solution. This approach addresses the critical bottlenecks of short‑reach interconnects in future super‑computing clusters and data‑center fabrics, offering a practical path toward dense, multi‑terabit per second optical I/O ecosystems.