Teaching Experiences using the RVfpga Package

The RVfpga course offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and the VeeR EL2, developed by Western Digital a few years ago and currently hosted by ChipsAlliance. This course is particularly aimed at educators and students in computer science, computer engineering, and related fields, enabling them to integrate practical RISC-V knowledge into their curricula. The course materials, which include detailed labs and setup guides, are available for free through the Imagination University Programme website. We have used RVfpga in different teaching activities and we plan to continue using it in the future. Specifically, we have used RVfpga as the main experimental platform in several bachelor/master degree courses; we have completed several final bachelor/master degree projects based on this platform; we will conduct a microcredential about processor design based on RVfpga; we have adapted RVfpga to a MOOC in the edX platform; and we have shared RVfpga worldwide through one-day hands-on workshops and tutorials. This paper begins by discussing how the RVfpga course matches the latest IEEE/ACM/AAAI computing curriculum guidelines. It then details various teaching implementations we have conducted over recent years using these materials. Finally, the paper examines other courses similar to RVfpga, comparing their strengths and weaknesses.

💡 Research Summary

The paper presents the RVfpga educational package, a comprehensive curriculum that combines the open‑source RISC‑V instruction set architecture with FPGA technology to teach computer architecture. It focuses on two main courses: the RVfpga course, which contains 20 laboratory modules, and the RVfpga‑SoC course, which adds five system‑on‑chip labs. The RVfpga labs guide students through C programming, RISC‑V assembly, function calls, image processing, Vivado project creation, I/O handling, seven‑segment display control, timer usage, interrupt‑driven I/O, serial bus communication, core configuration and performance counters, arithmetic and logical instructions, memory load/store operations, structural, data and control hazards, branch prediction, superscalar execution (for the EH1 core), adding new instructions, instruction cache design, and benchmarking with CoreMark and Dhrystone. The RVfpga‑SoC labs cover SoC initialization, running software on the SoC, introduction to SweRVolf and FuseSoC, building and executing the Zephyr RTOS, and running TensorFlow Lite on the SweRVolf core.

The authors map the content of these courses to the latest IEEE/ACM/AAAI computing curriculum guidelines (CS2023), showing that the package addresses virtually all knowledge units in the Architecture and Organization (AR) area: digital logic and FPGA design, machine‑level data representation, assembly‑level organization, memory hierarchy, interfacing and communication, functional organization (datapaths, pipelining, hazard detection), and performance/energy efficiency. The paper notes that topics such as heterogeneous architectures, secure processor design, and quantum architectures are not currently covered but could be added by extending the package with newer cores (e.g., VeeR EH2) or by incorporating RISC‑V bit‑manipulation extensions for cryptographic acceleration.

A series of real‑world teaching experiences are described. At Universidad Complutense de Madrid (UCM), the integrated systems architecture course uses both RVfpga and RVfpga‑SoC, providing students with Nexys A7 boards, a virtual machine with pre‑installed tools, and the Ripes visual simulator. The course spans five modules and nine labs, covering ISA review, processor design, memory hierarchy, I/O, and SoC design. Portland State University employs the RVfpga‑SoC course to teach SoC construction and Zephyr integration. The Ruppin Academic Center organized a RISC‑V hackathon using RVfpga labs, and the University of Barcelona incorporated selected labs into an introductory computer architecture class. The authors also report adapting the material to a massive open online course (MOOC) on edX, delivering one‑day hands‑on workshops, and creating a micro‑credential focused on processor design.

The paper compares RVfpga with other educational offerings such as Rocket‑Chip‑based courses and OpenHW Core IP curricula. RVfpga’s strengths lie in the breadth of hands‑on labs, the availability of real FPGA boards, the inclusion of both low‑level hardware design and high‑level software stacks, and the open‑source toolchain (RISC‑V GNU toolchain, Vivado, Ripes, Whisper, etc.). Its weaknesses are the current lack of advanced topics like secure enclaves, multi‑threaded cores, and quantum computing concepts. The authors suggest future work to incorporate VeeR EH2 for multi‑threading, add bit‑manipulation extensions for cryptographic labs, and develop new modules on heterogeneous and quantum architectures.

In conclusion, the RVfpga package provides a robust, scalable, and freely available platform for teaching modern computer architecture from gate‑level design to system‑level software. It aligns closely with contemporary curriculum standards, has been successfully deployed across multiple universities and instructional formats, and offers a solid foundation for further expansion into emerging architectural domains.