Substrate-Voltage-Controlled Temporal Nonlinearity in Ferroelectric FET-based Reservoir Computing

Physical reservoir computing exploits inherent nonlinearity and short-term memory of physical dynamics to achieve efficient processing of time-series data with extremely-low training cost. In this study, we demonstrate a ferroelectric field-effect transistor (FeFET)-based reservoir computing system with augmented temporal and spatial nonlinearity by utilizing both gate and substrate terminals as inputs. The ferroelectric polarization state in the next time step can additionally be controlled by modifying the electric field distribution in the gate stack of FeFET through a substrate input, enabling more diverse internal states compared with the case where inputs are applied only to the gate. To introduce a nonlinearity in the time domain, we introduce a delay between a gate input and a substrate input, which facilitates efficient nonlinear mixing between the current and past inputs. As a result, both the short-term memory and nonlinearity of the FeFET reservoir computing system are enhanced with an improved capability of feature extraction of complex input time-series. These findings demonstrate that introducing substrate input provides an additional degree of freedom for controlling ferroelectric polarization dynamics, enabling a flexible, energy-efficient, and highly integrable FeFET-based reservoir computing platform suitable for diverse time-series processing applications.

💡 Research Summary

This paper presents a novel ferroelectric field‑effect transistor (FeFET)‑based reservoir computing (RC) architecture that exploits both the gate and substrate terminals as independent inputs, introducing a deliberate delay between them to enhance temporal nonlinearity. Physical RC leverages the intrinsic dynamics of a physical system to perform computation with minimal training cost, but its performance is limited by the diversity of the system’s response to inputs. While previous FeFET‑based RC implementations used only gate voltage pulses to drive ferroelectric polarization switching, the authors recognize that this single‑input approach restricts the electric‑field distribution to a simple gate‑to‑drain transfer function, limiting the richness of internal states.

The study first characterizes how a substrate bias influences ferroelectric switching. By measuring polarization‑versus‑gate voltage (P‑Vg) curves under 0 V and –5 V substrate bias, they find that a negative substrate voltage markedly suppresses switching for negative gate pulses, while having little effect on positive gate pulses. MOS band‑diagram analysis reveals that a negative substrate bias raises the silicon band energy, depletes the hole accumulation layer, and consequently reduces the electric field across the ferroelectric layer during negative gate operation. This asymmetry demonstrates that substrate voltage provides a non‑linear, non‑additive control over polarization dynamics, offering an extra degree of freedom beyond the gate voltage.

Building on this insight, the authors construct a dual‑input FeFET RC system. Digital time‑series data are encoded as 4 µs triangular voltage pulses: the gate receives a 0.5 V offset with ±3 V amplitude, while the substrate receives a –2.5 V offset with ±2.5 V amplitude. The drain is biased at 0.3 V and the source at 0 V. Drain and source currents are sampled every 40 ns, yielding 100 points per terminal per time step and a total of 200 virtual nodes (N = 200). To explore temporal mixing, the substrate pulses are delayed by τ_sub time steps relative to the gate pulses.

Training employs ridge regression on the internal state matrix X (N × L) generated from 500 time steps of each of ten 1000‑step sequences (the first 500 steps are discarded as wash‑out). The system is evaluated on three benchmark tasks: short‑term memory (STM), temporal exclusive‑OR (XOR), and the more demanding NARMA‑10. Performance is quantified by the computational capacity C, derived from the coefficient of determination r² between target and output over a horizon D = 9.

Results show that without substrate input, or with simultaneous substrate and gate pulses, there is no significant improvement over the single‑gate configuration. However, introducing a delay of τ_sub = 1–3 steps markedly increases both C_MC (memory capacity) and C_XOR (non‑linear capacity). Larger delays cause a slight performance drop, indicating an optimal delay window where past inputs are sufficiently mixed without losing correlation. Waveform analysis confirms that delayed substrate input creates distinct drain‑current signatures for different input histories (e.g., (0,0,0) vs. (1,0,0) three steps earlier), whereas the no‑delay case yields nearly identical waveforms, explaining the observed capacity gains.

The authors conclude that substrate voltage, when used as a delayed second input, enriches the internal state space of FeFET reservoirs by providing independent control over ferroelectric polarization dynamics. This dual‑input, temporally delayed scheme simultaneously enhances short‑term memory and nonlinear processing, offering a highly energy‑efficient, CMOS‑compatible platform for complex time‑series tasks. The work opens avenues for scaling to larger FeFET arrays, reconfigurable reservoir topologies, and application‑specific tailoring in fields such as sensor data streaming, real‑time signal processing, and edge‑AI inference.