Report for NSF Workshop on AI for Electronic Design Automation

This report distills the discussions and recommendations from the NSF Workshop on AI for Electronic Design Automation (EDA), held on December 10, 2024 in Vancouver alongside NeurIPS 2024. Bringing together experts across machine learning and EDA, the workshop examined how AI-spanning large language models (LLMs), graph neural networks (GNNs), reinforcement learning (RL), neurosymbolic methods, etc.-can facilitate EDA and shorten design turnaround. The workshop includes four themes: (1) AI for physical synthesis and design for manufacturing (DFM), discussing challenges in physical manufacturing process and potential AI applications; (2) AI for high-level and logic-level synthesis (HLS/LLS), covering pragma insertion, program transformation, RTL code generation, etc.; (3) AI toolbox for optimization and design, discussing frontier AI developments that could potentially be applied to EDA tasks; and (4) AI for test and verification, including LLM-assisted verification tools, ML-augmented SAT solving, security/reliability challenges, etc. The report recommends NSF to foster AI/EDA collaboration, invest in foundational AI for EDA, develop robust data infrastructures, promote scalable compute infrastructure, and invest in workforce development to democratize hardware design and enable next-generation hardware systems. The workshop information can be found on the website https://ai4eda-workshop.github.io/.

💡 Research Summary

The document is a comprehensive report summarizing the discussions and recommendations from the NSF Workshop on AI for Electronic Design Automation (EDA) held on December 10, 2024 in Vancouver, co‑located with NeurIPS 2024. The workshop brought together leading researchers from machine learning and traditional EDA to explore how emerging AI techniques—large language models (LLMs), graph neural networks (GNNs), reinforcement learning (RL), neurosymbolic methods, and generative AI—can accelerate and democratize the chip design process.

Four thematic tracks were examined.

1. AI for Physical Synthesis and Design for Manufacturing (DFM). Participants highlighted the multi‑objective nature of placement, routing, and manufacturability, the explosion of design‑rule constraints, and the long turnaround times associated with advanced nodes (3 nm, 2 nm). Current AI efforts include RL‑based macro placement, surrogate models for fast timing/power estimation, LLM‑driven DRC rule generation, and generative models that propose layout alternatives. The main blockers are poor generalization across designs and process nodes, scarcity of high‑quality training data, and the heavy compute budgets required for large models. Recommendations focus on open‑source datasets, hybrid AI‑traditional pipelines, and scalable compute resources.

2. AI for High‑Level and Logic‑Level Synthesis (HLS/LLS). The session addressed the translation from high‑level behavioral code to RTL, a step traditionally fraught with manual pragma insertion, performance prediction, and iterative synthesis loops. Demonstrated approaches involve GNNs for power‑area‑timing prediction, LLMs for pragma recommendation and even natural‑language‑to‑RTL generation (NL2RTL), and deep‑learning‑enhanced optimization loops. Show‑stoppers mirror those in DFM: domain shift when tools or kernels change, and a lack of labeled data. Opportunities were identified in multimodal fusion (text + graph), transfer learning, synthetic data generation, and meta‑learning to adapt models quickly.

3. AI Toolbox for Optimization and Design. This track turned the lens on AI itself, noting that most ML methods rely on offline datasets and well‑defined objective functions. Participants advocated for uncertainty quantification, black‑box optimization, RL‑based design‑space exploration, and especially LLM‑driven agents that can orchestrate end‑to‑end design flows—from data collection through tool invocation to verification. Emphasis was placed on hybrid approaches that combine gradient‑based optimization with learned surrogates, and on building modular, reusable AI components that can be plugged into existing EDA environments.

4. AI for Test and Verification. The final theme explored how AI can improve verification efficiency and robustness. Topics included LLM‑assisted generation of testbenches and fuzzing programs, a new technique called Generalized Quick Error Detection (G‑QED) for rapid bug localization, and ML‑augmented SAT solving for constraint solving. Security concerns were raised: AI‑generated test artifacts could inadvertently introduce vulnerabilities, and the reliability of AI‑driven verification must be rigorously validated.

Across all themes, the report distilled a set of strategic recommendations for the NSF:

• Foster cross‑disciplinary collaboration through shared benchmarks, open‑source tools, joint research programs, and community challenges.
• Invest in foundational AI research tailored to EDA, with a focus on explainability, robustness, and scalability.
• Develop robust data infrastructures that enable efficient extraction, curation, and sharing of design data, while respecting IP constraints.
• Promote scalable compute infrastructure (GPU/TPU clusters, cloud resources) and encourage hybrid AI‑algorithmic solutions.
• Support workforce development via interdisciplinary graduate programs, bootcamps, and summer schools to train a new generation of AI‑EDA experts.

The report concludes that realizing AI’s transformative potential in chip design will require coordinated effort to overcome data scarcity, generalization challenges, and integration hurdles. By addressing these areas, AI can dramatically shorten design cycles, democratize hardware innovation, and enable the creation of next‑generation, energy‑efficient computing systems.