ATLAS MDT TDC Simulations for LHC Run3 and HL-LHC

The Large Hadron Collider (LHC) started the Run 3 operation in 2022, and the peak instantaneous luminosity in Run 3 may reach 3 x 10^34 cm-2s-1. The ATLAS Monitored Drift Tube (MDT) chambers are the main component of the precision tracking system in the ATLAS muon spectrometer. It is important to understand any potential issues with the MDT Front-End (FE) readout electronics for an expected level-1 (L1) trigger rate of 100 kHz and a complex deadtime of over 5% for Run 3 operations. We use raw data collected in 2022 to emulate the expected hit rates in MDT chambers and perform a realistic simulation on the ATLAS Muon TDC (Time-to-Digital Converter) (AMT) chip with the current configuration. We study the AMT chip performances by analyzing the trigger/L1/readout buffer occupancies and hit loss fractions under different luminosities with L1 rate of 100 kHz by using the Modelsim software. The hit loss fraction of the hottest MDT chamber (BIL3C05) is lower than 5% due to FE readout, even at a luminosity of 5.01 x 10^34 cm-2s-1 with a deadtime of 5% and a L1 rate of 100 kHz, indicating that AMT can operate under Run 3 conditions without problems. The MDT trigger and readout electronics will be replaced for triggerless readout during High-Luminosity LHC (HL-LHC) runs. We also simulate the AMT behavior in the triggerless mode up to 7.44 x 10^34 cm-2s-1 and propose possible AMT configurations in case some FE electronics could not be replaced during the long shutdown 3 (LS3).

💡 Research Summary

The paper presents a comprehensive study of the ATLAS Monitored Drift Tube (MDT) front‑end readout electronics, focusing on the performance of the AMT‑3 Time‑to‑Digital Converter (TDC) chip under the demanding conditions expected for LHC Run 3 and the future High‑Luminosity LHC (HL‑LHC). Using raw MDT data collected in 2022, the authors reconstructed realistic hit‑rate patterns for individual chambers, normalized them to a range of instantaneous luminosities (from 1.08 × 10³⁴ cm⁻² s⁻¹ up to 5.01 × 10³⁴ cm⁻² s⁻¹ for Run 3 and up to 7.44 × 10³⁴ cm⁻² s⁻¹ for HL‑LHC). They then fed these hit streams into a behavioral ModelSim simulation of the AMT‑3 chip, which faithfully reproduces the chip’s architecture: 24 channels, each with an Amplifier‑Shaper‑Discriminator (ASD) front‑end, a 40 MHz LHC clock multiplied to 80 MHz by a PLL, and a fine‑time measurement resolution of about 250 ps.

Two operating modes are examined. In the traditional triggered mode, a 1300 ns time window is opened for each Level‑1 Accept (L1A) and a fixed 100 kHz L1 trigger rate is imposed. The authors model dead‑time with two components: a simple dead‑time of 4 Bunch Crossings (≈100 ns) after each L1A, and a more realistic “complex” dead‑time implemented via a leaky‑bucket algorithm. The bucket parameters (S/R) are varied from 0.1 % to 10 % to emulate different levels of front‑end buffer congestion. The simulation tracks buffer occupancies in the per‑channel 320‑word FIFO and the shared 256‑word L1 buffer, as well as the fraction of hits lost due to overflow.

Results show that under the current ATLAS configuration (bucket 2: S/R = 7/351, the most stringent setting), even the hottest chamber (BIL3C05) experiences a hit‑loss fraction below 5 % at a luminosity of 5.01 × 10³⁴ cm⁻² s⁻¹, a dead‑time of 5 % and a 100 kHz L1 rate. Buffer occupancies remain well within limits, confirming that the AMT‑3 can comfortably meet Run 3 requirements.

For HL‑LHC, the study switches to a trigger‑less mode where the complex dead‑time is disabled and all hits are streamed directly to the FIFO. In this mode the chip can operate with a reduced data volume by using single‑edge timing (only the leading edge is recorded), halving the bandwidth demand. Simulations up to 7.44 × 10³⁴ cm⁻² s⁻¹ indicate hit‑loss fractions below 3 % even for chambers with the highest projected rates (≈80 kHz per channel). The trigger‑less configuration also relaxes the need for the 1300 ns time window; a shorter 800 ns window is sufficient for chambers with lower rates, further reducing latency.

Recognizing that not all front‑end electronics may be replaced during LS3, the authors propose three practical AMT‑3 configuration adjustments for the HL‑LHC era: (1) halve the FIFO depth to 160 words and adopt single‑edge measurement to cut data throughput; (2) relax the complex dead‑time bucket ratio to S/R ≈ 1 % to mitigate burst‑induced pressure on buffers; and (3) shrink the L1 time window for low‑rate chambers to 800 ns, decreasing overall system dead‑time. These options preserve the existing hardware while ensuring acceptable performance under the extreme HL‑LHC conditions.

In summary, the paper demonstrates that the existing AMT‑3 chip, as presently configured, satisfies the Run 3 specifications with ample margin, and that with modest firmware or configuration changes it can also meet the much higher hit rates and trigger‑less operation required for HL‑LHC. This validates the robustness of the ATLAS MDT readout chain and provides a clear roadmap for any necessary upgrades before the long shutdown LS3.