End-to-End Fidelity Analysis of Quantum Circuit Optimization: From Gate-Level Transformations to Pulse-Level Control

We present a comprehensive analysis of quantum circuit fidelity across the full compilation stack, from high-level gate optimization through pulse-level control. Using a modular integration framework connecting a C++ circuit optimizer with Lindblad-based pulse simulation, we systematically evaluate the fidelity impact of four optimization passes: gate cancellation, commutation, rotation merging, and identity elimination, on IQM Garnet hardware parameters. Our simulation campaign spanning 371 circuit runs reveals that gate cancellation provides the most significant improvement (68% of circuits improved, 14,024 gates eliminated), while pulse duration exhibits the strongest negative correlation with process fidelity ($r = -0.74$, $R^2 = 0.55$). We validate these findings through hardware execution on the IQM Resonance Garnet 20-qubit processor, demonstrating 70% gate reduction on QFT circuits with 100% job success rate (8 executions). Our open-source framework enables reproducible benchmarking of quantum compilation pipelines.

💡 Research Summary

This paper introduces “qco‑integration,” a modular framework that connects a C++‑based quantum circuit optimizer with a Python pulse‑synthesis tool (QubitPulseOpt) via OpenQASM 3.0 and JSON. The authors use the framework to evaluate the end‑to‑end impact of four gate‑level optimization passes—gate cancellation, commutation analysis, rotation merging, and identity elimination—on the process fidelity of circuits compiled for the IQM Garnet 20‑qubit superconducting processor.

A corpus of 371 benchmark circuits (GHZ state preparation, Quantum Fourier Transform, QAOA, and randomly generated circuits) is processed through a five‑stage pipeline: parsing, optimization, SABRE routing, pulse compilation (with calibrated 20 ns single‑qubit and 40 ns two‑qubit gate durations), and Lindblad‑based noise simulation using realistic T₁≈37 µs and T₂≈9.6 µs parameters. Six experimental configurations are explored, ranging from a baseline with no optimizations to combinations of passes, routing impact, noise‑sensitivity studies, and scaling analyses. Two fidelity metrics are reported: process fidelity (trace overlap of implemented vs. target unitaries) and state fidelity (overlap with a target state).

Simulation results show an average process fidelity of 0.68 ± 0.22 across all circuits and a mean gate‑count reduction of 23.1 %. Gate cancellation is the most effective pass, removing 14 024 gates (68 % of circuits improved) and contributing the largest fidelity gains with minimal computational overhead. Rotation merging eliminates 6 512 gates, especially benefiting circuits with consecutive rotations such as QFT and QAOA. Commutation analysis alone does not reduce gate count but creates opportunities for subsequent cancellation; the optimal pass ordering is cancel → commute → rotate. Identity elimination yields only 55 gate removals (9 % improvement rate) and is deemed low‑impact for latency‑sensitive workloads.

Correlation analysis reveals that total pulse duration is the strongest predictor of fidelity loss (Pearson r = ‑0.743, R² = 0.553), followed by input gate count, circuit depth, and number of qubits. Two‑qubit gate errors dominate the error budget, accounting for roughly 60 % of fidelity degradation. Larger circuits (e.g., 12‑qubit GHZ) exhibit steep fidelity declines, underscoring the cumulative effect of decoherence and gate errors in the NISQ regime.

Hardware validation is performed on the IQM Resonance Garnet processor. Eight quantum jobs (GHZ with 4, 8, 12 qubits and a 4‑qubit QFT) are executed both in their original and optimized forms, each with 160 shots. The QFT circuit experiences a 70 % gate‑count reduction (30 → 9 gates) and an 85.7 % depth reduction (21 → 3 layers), confirming the simulation‑predicted optimization potential. GHZ circuits, already near‑minimal, show no gate reduction but a modest (~12 %) fidelity improvement, suggesting that optimizer‑driven remapping can occasionally enhance hardware performance. All jobs complete successfully (100 % success rate).

The authors discuss practical implications: prioritize early and repeated gate cancellation, use commutation to expose further cancellations, apply rotation merging for rotation‑heavy algorithms, and consider de‑emphasizing identity elimination in time‑critical pipelines. Minimizing total pulse duration—through topology‑aware synthesis and parallel execution—emerges as a key strategy for improving NISQ fidelity.

Limitations include the modest shot count (160), reliance on a single device session, use of an approximate Lindblad decay model, and a hardware validation set that is smaller than the simulation corpus. Future work should expand to multiple quantum hardware platforms (IBM, Google, Rigetti), increase circuit diversity, incorporate more sophisticated noise models, explore dynamic pass ordering, and develop pulse‑level parallelization techniques to further shrink execution time.

In conclusion, the paper delivers a reproducible, open‑source framework for end‑to‑end fidelity analysis of quantum compilation, validates its predictions on real hardware, and quantifies how specific gate‑level optimizations translate into tangible fidelity gains. The findings provide concrete guidance for compiler designers aiming to maximize performance on near‑term quantum devices.