AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance

Graph neural network (GNN) inference faces significant bottlenecks in preprocessing, which often dominate overall inference latency. We introduce AutoGNN, an FPGA-based accelerator designed to address these challenges by leveraging FPGA’s reconfigurability and specialized components. AutoGNN adapts to diverse graph inputs, efficiently performing computationally intensive tasks such as graph conversion and sampling. By utilizing components like adder trees, AutoGNN executes reduction operations in constant time, overcoming the limitations of serialization and synchronization on GPUs. AutoGNN integrates unified processing elements (UPEs) and single-cycle reducers (SCRs) to streamline GNN preprocessing. UPEs enable scalable parallel processing for edge sorting and unique vertex selection, while SCRs efficiently handle sequential tasks such as pointer array construction and subgraph reindexing. A user-level software framework dynamically profiles graph inputs, determines optimal configurations, and reprograms AutoGNN to handle varying workloads. Implemented on a 7$n$m enterprise FPGA, AutoGNN achieves up to 9.0$\times$ and 2.1$\times$ speedup compared to conventional and GPU-accelerated preprocessing systems, respectively, enabling high-performance GNN preprocessing across diverse datasets.

💡 Research Summary

Graph neural networks (GNNs) have become a cornerstone of many modern AI applications, yet their inference pipelines are often dominated by preprocessing overhead. The authors identify two major preprocessing tasks: (i) graph format conversion, typically from a storage‑efficient COO representation to a computation‑friendly CSC format, and (ii) graph sampling, which extracts a subgraph to mitigate node explosion. Both tasks involve heavy sorting, reduction, and synchronization operations that are poorly suited to GPUs because they require frequent locks, atomic updates, and irregular memory accesses, leading to serialization and high latency.

AutoGNN is introduced as a dedicated FPGA accelerator that tackles these bottlenecks by exploiting the reconfigurability and fine‑grained parallelism of modern FPGAs. The hardware architecture consists of two core components: Unified Processing Elements (UPEs) and Single‑Cycle Reducers (SCRs). UPEs combine prefix‑sum and routing techniques to perform edge ordering (sorting by destination then source) and unique vertex selection within a single logic block. By using a parallel compare‑exchange network and multiple memory banks, UPEs achieve near‑constant‑time performance for tasks that would otherwise require O(log N) or O(N) steps on a GPU. SCRs address the inherently sequential parts of preprocessing—pointer array construction, vertex/edge counting, and subgraph reindexing—by deploying multiple comparators and an adder‑tree that aggregates results in a single clock cycle, thereby eliminating the need for software‑level locks.

A software stack runs on the host CPU, profiling the input graph (edge count, average degree, sampling ratio, etc.) and feeding these metrics into a cost model that predicts the optimal number of UPEs and SCRs as well as their placement on the FPGA fabric. When the model determines that a different configuration would yield better performance, only the affected hardware modules are re‑programmed, keeping reconfiguration latency low. This dynamic adaptation allows AutoGNN to handle a wide spectrum of graphs, from sparse social networks to dense recommendation‑system graphs, without over‑provisioning resources.

The authors implemented the full pipeline on a 7 nm enterprise‑class FPGA evaluation board and evaluated it on eleven publicly available graph datasets ranging from a few hundred thousand to hundreds of millions of edges. Compared to a state‑of‑the‑art CPU‑based preprocessing pipeline, AutoGNN achieves up to 9.0× speedup; against a GPU‑accelerated baseline (RTX 3090 with DGL), it delivers up to 2.1× improvement. The most pronounced gains appear in the edge‑ordering stage, where the FPGA’s parallel sorting outperforms GPU implementations by an order of magnitude on high‑density graphs. Power consumption is also reduced by roughly threefold relative to the GPU solution, highlighting the energy‑efficiency benefits of the custom hardware.

Key insights from the work include: (1) a clear separation of GNN preprocessing into parallelizable (sorting, unique selection) and non‑parallelizable (counting, reindexing) sub‑tasks, each of which can be mapped to a specialized hardware primitive; (2) the exploitation of FPGA adder‑tree logic to achieve O(1) reduction latency, thereby removing synchronization bottlenecks that plague GPU implementations; (3) a runtime‑aware reconfiguration strategy that tailors the accelerator’s resource allocation to the characteristics of each input graph, ensuring consistent performance across diverse workloads.

Overall, AutoGNN demonstrates that dedicated, dynamically reconfigurable hardware can dramatically shrink the preprocessing portion of GNN inference pipelines, making real‑time deployment of GNNs feasible for latency‑critical domains such as autonomous driving, high‑energy physics, and large‑scale recommendation systems. Future directions suggested by the authors include extending SCR functionality to support dynamic graph updates, scaling the architecture across multiple FPGAs for even larger graphs, and integrating the accelerator more tightly with downstream GNN inference engines to form a seamless end‑to‑end solution.