KEK Accelerator Test Facility Low-Level RF and Timing Systems

The KEK Accelerator Test Facility (ATF) is a dedicated testbed for nanobeam technologies in support of the International Linear Collider (ILC). Stable pulsed operation requires synchronization of the facility timing system with the Low-Level RF (LLRF) system. The timing system distributes trigger and gate signals to key subsystems, including the DAQ, klystrons, laser systems, pulsed kicker magnets, and interlocks. The LLRF system provides phase-coherent RF references and facility-wide clock distribution for synchronization. Achieving ~100 fs-level synchronization depends critically on the phase-noise power spectral density (PN-PSD) of the distributed clock signals and on preserving this performance throughout the distribution network. We present facility-wide measurements of the KEK ATF LLRF clock PN-PSD and discuss the resulting synchronization floor imposed by the stability of the ATF Linac and Damping Ring signal generators.

💡 Research Summary

The KEK Accelerator Test Facility (ATF) serves as a dedicated platform for nanobeam experiments supporting the International Linear Collider. Precise synchronization between the timing system and the low‑level RF (LLRF) system is essential for stable pulsed operation. This paper presents a facility‑wide characterization of the LLRF clock distribution network by measuring the phase‑noise power spectral density (PN‑PSD) from 1 Hz to 10 MHz offset frequencies and converting these spectra into integrated rms time jitter values.

The LLRF architecture uses two Agilent E8663B signal generators (SGs). The Linac SG acts as the master, producing a 1.428 GHz continuous wave that is multiplied to generate the 2.856 GHz klystron reference and sub‑harmonics at 357 MHz and 178.5 MHz. The Damping Ring (DR) SG provides a 714 MHz clock that feeds the DR RF system and a frequency‑ramp electronics chain. Both SGs are locked to a low‑noise 10 MHz reference and distribute their signals via phase‑stabilized optical fiber (PSOF) with separate electro‑optic (E/O) and optic‑electric (O/E) conversion stages for each subsystem.

Measurements were performed with an Agilent E5052B Signal Source Analyzer in PLL carrier‑tracking/direct‑homodyne mode. For the Linac klystron branch, the SG’s intrinsic jitter is 70 fs rms when frequency modulation (FM) is disabled; after up‑conversion, amplification, and splitting, the integrated jitter remains around 120 fs. Enabling FM (10 kHz bandwidth) raises the jitter to 1.64 ps at the SG output, but the conversion chain slightly improves it to ~1.5 ps at the klystron inputs. Individual klystron branches show jitter variations (≈120–190 fs FM‑off, ≈1.45–1.72 ps FM‑on) due to differing E/O/O/E converters and feedback configurations.

In the DR sector, the 714 MHz clock exhibits 90 fs rms jitter with FM disabled. When the frequency‑ramp electronics and FM are engaged, the jitter jumps to ≈2 ps, dominated by the external PLL that controls the ramp. Down‑conversion to 357 MHz and 178.5 MHz introduces additional jitter (250 fs/2.64 ps for FM‑off and 1.36 ps/2.92 ps for FM‑on). The DR SG’s 10 MHz reference shows a higher jitter (≈520 fs) than the Linac reference because of internal daisy‑chain processing.

The Final Focus (FF) receives the DR clock, which after E/O/O/E conversion and FM‑on operation degrades to ≈5.7 ps rms. The signal is up‑converted to a 6.453 GHz C‑band LO used for cavity beam position monitor (cBPM) down‑conversion; the LO inherits the same jitter level.

Overall, the Linac distribution achieves sub‑100 fs performance under nominal conditions, confirming that the optical fiber and conversion stages preserve low‑jitter characteristics. In contrast, the DR ramp‑generation feedback loop is the primary source of several‑picosecond jitter, and this degradation propagates to downstream FF systems. The authors conclude that further jitter reduction across the entire facility hinges on redesigning the DR ramp‑generation architecture—optimizing loop bandwidth, implementing noise shaping, improving actuator placement, and relocating critical electronics. Such upgrades are expected to extend sub‑100 fs synchronization stability to all ATF sections even during operational FM‑on modes.