Weight-four parity checks with silicon spin qubits

Recent advances in coherent spin shuttling have made sparse semiconductor spin qubit arrays an appealing solid-state platform to realize quantum processors. The dynamic and long-range connectivity enabled by shuttling is also essential for many quantum error-correction (QEC) schemes. Here, we demonstrate a silicon spin-qubit device that comprises a shuttling bus for coherently transporting qubits that can interact at four isolated locations we call bus stops. We dynamically populate the array and tune all single- and two-qubit operations using shuttling and quantum non-demolition (QND) spin measurements, without access to charge sensing in most of the device. We achieve universal control of the effective five-qubit processor and select the connectivity required to form a surface-code stabilizer plaquette that supports X- and Z-type parity checks up to weight-four. We use the parity checks to generate multi-qubit entanglement between all qubit combinations in the array and report the genuine entanglement of a five-qubit Greenberger-Horne-Zeilinger (GHZ) state, constituting the largest such state ever constructed with gate-defined semiconductor spins. This work opens immediate opportunities to pursue QEC experiments with spin qubits, and the protocols developed here lay the groundwork for the modular calibration and operation of sparse spin qubit arrays.

💡 Research Summary

In this work the authors demonstrate a silicon‑based quantum processor that leverages coherent electron‑spin shuttling to achieve long‑range, programmable connectivity in a sparsely populated quantum‑dot array. The device consists of five spin qubits defined in an isotopically purified 28Si/SiGe heterostructure: one read‑out ancilla (R1), one mobile ancilla (A1) that can be shuttled along a 15‑gate “bus”, and four data qubits (D1‑D4) located at four dedicated “bus stops”. The bus provides a physical pathway for the mobile ancilla to be positioned adjacent to any data qubit, enabling two‑qubit exchange interactions without the need for static nearest‑neighbor coupling.

A key technical challenge is that the on‑chip charge sensor (a single‑electron transistor) can only sense the first bus stop, leaving the remaining three out of direct charge‑sensing range. To overcome this, the authors develop a remote‑tuning protocol that uses the spin degree of freedom itself as a probe. By preparing the mobile ancilla in a superposition, shuttling it to a distant bus stop, allowing a controlled dwell time, and then shuttling it back to the read‑out zone, they extract the phase accumulated due to coherent tunneling. This phase encodes the effective double‑dot detuning (vε) and average potential (vU) of the local two‑electron system, allowing reconstruction of charge‑stability diagrams and virtual‑gate matrices for each bus stop without direct charge detection.

With the virtual‑gate calibration in place, the authors tune the exchange coupling between the mobile ancilla and each data qubit by modulating the barrier gates at the bus stops. Exchange rates up to ~10 MHz are achieved, sufficient for resonant controlled‑rotation (CROT) and adiabatic controlled‑phase (CZ) gates, providing a universal two‑qubit entangling primitive. Coherence times of all qubits exceed 100 µs under dynamical decoupling, comfortably longer than the 10 µs single‑shot read‑out time, enabling mid‑circuit, quantum‑non‑demolition (QND) measurements.

The full processor operation proceeds as follows: (1) all four data qubits are loaded into the bus stops in mixed states via repeated shuttling of the ancilla; (2) a QND initialization sequence, employing real‑time feedback, prepares the ancilla and data qubits in the ground state |0⟩ (with the read‑out ancilla R1 initialized to |1⟩); (3) arbitrary single‑qubit rotations are performed using electric‑dipole spin resonance (EDSR) driven by a bottom‑gate microwave antenna; (4) two‑qubit gates are enacted by bringing the mobile ancilla into proximity with a selected data qubit and pulsing the exchange interaction; (5) multi‑qubit QND read‑out extracts up to five classical bits per cycle, and repeated QND rounds improve measurement fidelity. The total experimental cycle time is ≈300 µs, dominated by the PSB read‑out integration.

Using this toolbox the authors implement both X‑type and Z‑type weight‑four stabilizer measurements, the essential building blocks of the surface code. By sequentially entangling the mobile ancilla with each of the four data qubits, they generate a five‑qubit Greenberger‑Horne‑Zeilinger (GHZ) state. Full state tomography and multi‑round QND verification confirm genuine five‑qubit entanglement—the largest GHZ state reported for gate‑defined semiconductor spins to date.

From an architectural perspective, the work validates several long‑standing advantages of sparse spin‑qubit layouts: (i) residual exchange between idle neighboring spins is essentially eliminated, reducing crosstalk; (ii) lower qubit density eases routing of control lines and diminishes capacitive cross‑talk, lowering calibration overhead; (iii) read‑out can be decoupled from the qubit plane, avoiding bulky charge‑sensor or resonator structures. Moreover, the connectivity graph realized by the shuttling bus and bus stops exactly matches the four‑qubit stabilizer plaquette required for a surface‑code tile, demonstrating that a modest extension to multiple buses could support a full 2‑D surface‑code lattice.

In summary, the paper provides a comprehensive experimental demonstration that coherent spin shuttling enables modular calibration, universal control, and high‑fidelity multi‑qubit operations in a sparsely populated silicon spin‑qubit processor. The ability to perform weight‑four parity checks and generate a five‑qubit GHZ state paves the way toward scalable quantum error correction with semiconductor spins, offering a concrete pathway from few‑qubit prototypes to fault‑tolerant quantum computers.