Optimal Software Pipelining using an SMT-Solver

Software Pipelining is a classic and important loop-optimization for VLIW processors. It improves instruction-level parallelism by overlapping multiple iterations of a loop and executing them in parallel. Typically, it is implemented using heuristics. In this paper, we present an optimal software pipeliner based on a Satisfiability Modulo Theories (SMT) Solver. We show that our approach significantly outperforms heuristic algorithms and hand-optimization. Furthermore, we show how the solver can be used to give feedback to programmers and processor designers on why a software pipelined schedule of a certain initiation interval is not feasible.

💡 Research Summary

The paper presents a novel approach to the classic problem of software pipelining (SWP) for Very Long Instruction Word (VLIW) processors by formulating it as a Satisfiability Modulo Theories (SMT) problem and solving it with a modern SMT solver. The authors begin by outlining the unique challenges of VLIW compilation: all scheduling decisions must be made at compile time, the compiler must keep a large number of issue slots busy, and the generated schedule directly determines execution performance. Traditional solutions rely on heuristic algorithms such as Iterative Modulo Scheduling (IMS) and Swing Modulo Scheduling, which provide good but non‑optimal results, or on integer‑programming formulations that are often too costly for real‑world code bases.

The core contribution is a precise encoding of the SWP constraints into Boolean and integer variables that can be processed by an SMT engine. For each operation they introduce an integer variable Cycle_o indicating the cycle at which the operation is issued, and a set of Boolean variables Slot_o,s that select the exact issue slot. Additional Boolean variables Connected_c,op,b and Connected_c,b,wp model the routing of data from issue‑slot output ports through buses to register‑file write ports. The constraints enforce (1) valid cycle ranges, (2) exactly‑one‑slot assignment per operation, (3) exclusive use of each slot within the same modulo‑II cycle, (4) satisfaction of all data, anti‑, and output dependencies using the classic modulo‑scheduling inequality Cycle(o2) ≥ Cycle(o1) + l − d·II, (5) correct bus‑to‑port connections for each data‑flow edge, (6) at most one connection per bus per modulo cycle, and (7) at most one connection per register‑file write port per modulo cycle.

The algorithm proceeds by first computing a lower bound on the initiation interval (II) from resource and dependency analysis, then estimating a lower and upper bound on the number of pipeline stages (NumStages). The upper bound is derived by constructing a graph where each edge weight reflects the maximum permissible distance between two operations given the current II, applying the Floyd‑Warshall algorithm to find the longest such distance d, and setting the stage bound to ⌈d·II⌉. With these parameters fixed, the SMT problem is generated and submitted to the solver. If the solver returns SAT, the satisfying assignment is decoded into a prolog, kernel, and epilog schedule. If UNSAT, the solver’s unsatisfiable core is examined; the paper demonstrates how this core can be presented to developers, pinpointing, for example, an overloaded register‑file write port that makes a particular II infeasible. The algorithm then either increases the number of stages or the II and repeats the process, effectively performing an exhaustive search for the minimal feasible II.

The authors evaluated the method on more than 400 software‑pipelined loops extracted from firmware for two generations of Intel VLIW signal‑processing processors. Compared with state‑of‑the‑art heuristic schedulers and hand‑tuned schedules, the SMT‑based approach achieved a geometric mean speed‑up of 1.08× and a maximum speed‑up of 1.22×, while increasing code size by less than 1 %—a dramatic improvement over full loop unrolling, which would multiply code size severalfold. Moreover, the unsat‑core feedback mechanism provides actionable insight for both compiler writers and hardware architects, enabling design‑time decisions such as adding additional write ports or restructuring code to reduce register pressure.

In conclusion, the paper demonstrates that encoding software pipelining as an SMT problem yields optimal schedules for realistic VLIW workloads within practical solving times, surpasses heuristic methods, and offers a valuable diagnostic tool for architecture‑software co‑design. Future work is suggested in extending the model to incorporate register‑pressure constraints directly, handling multiple optimization objectives (e.g., power, area), and exploring incremental solving techniques to further accelerate the search for optimal II values.