SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence

Current methods for converting circuit schematic images into machine-readable netlists struggle with component recognition and connectivity inference. In this paper, we present SINA, an open-source, fully automated circuit schematic image-to-netlist generator. SINA integrates deep learning for accurate component detection, Connected-Component Labeling (CCL) for precise connectivity extraction, and Optical Character Recognition (OCR) for component reference designator retrieval, while employing a Vision-Language Model (VLM) for reliable reference designator assignments. In our experiments, SINA achieves 96.47% overall netlist-generation accuracy, which is 2.72x higher than state-of-the-art approaches.

💡 Research Summary

This paper presents SINA, an open-source, fully automated pipeline for converting circuit schematic images into machine-readable, SPICE-compatible netlists. The core challenge addressed is the inability of current Electronic Design Automation (EDA) workflows and AI models to directly utilize the vast repository of circuit knowledge locked within visual schematics found in research papers, textbooks, and online resources. Existing automated methods suffer from inaccuracies in component recognition, unreliable connectivity inference, and poor reference designator assignment.

SINA tackles these limitations through a sophisticated, multi-stage framework that synergistically combines different artificial intelligence and image processing techniques. The pipeline consists of four main stages: Component Detection, Connectivity Inference, Reference Designator Extraction & Assignment, and final Netlist Generation.

In the first stage, Component Detection, a YOLOv11-based deep learning model identifies and localizes all circuit components (e.g., resistors, transistors, voltage sources) within the image, outputting bounding boxes, component types, and unique IDs. To enhance reliability, an independent verification step employs a Vision-Language Model (VLM), specifically GPT-4o, to analyze the schematic and predict component types and counts. The concordance between the YOLO detections and the VLM analysis is calculated, flagging any discrepancies for user review.

The second stage, Connectivity Inference, determines how the detected components are electrically connected. After masking out the detected components, only the wiring remains. A Connected-Component Labeling (CCL) algorithm segments this wiring into distinct connected regions. These regions are filtered to remove artifacts (like small stubs or gaps), and only regions connecting two or more components are retained as valid electrical nodes. Electrically equivalent nodes (like multiple ground symbols) are merged. The system then establishes a precise mapping by finding intersection points between component terminal locations and these node regions, defining exactly which component pin connects to which circuit node.

The third stage handles Reference Designator Extraction and Assignment. EasyOCR is first used to extract all textual annotations (e.g., “R1”, “10k”, “Vdd”) from the schematic image. These text strings are initially associated with components based on spatial proximity. The final, context-aware assignment is performed by the VLM (GPT-4o). The VLM synthesizes three key pieces of information: the OCR-extracted text, the component-to-node connectivity map from the previous stage, and the original schematic image for visual context. This allows the VLM to correctly assign designators (like “Q1” to a specific transistor) and values (like “1.2V” to a voltage source), resolving ambiguities that pure OCR cannot.

Finally, in the Netlist Generation stage, the VLM formats all the gathered information—the definitively assigned component designators and values, along with their node connections—into a standard SPICE netlist syntax, producing the final machine-readable output.

The authors constructed an open-source benchmark comprising schematics of varying styles and complexities for evaluation. The component detection model, fine-tuned on a custom dataset of over 700 annotated schematics, achieved an F1 score of 96.47% on a test set of 75 schematics with over 1,000 components. For end-to-end netlist generation, SINA was compared against Masala-CHAI, the only other available open-source tool for this task, on a curated set of 40 test circuits. SINA significantly outperformed Masala-CHAI across all metrics: text extraction (97.55% vs. 95.09%), component detection F1 score (99.6% vs. 62.4%), circuit structure accuracy (99.3% vs. 59.8%), and overall netlist generation accuracy (96.47% vs. 35.5%). This represents a 2.72x improvement in overall accuracy.

In conclusion, SINA demonstrates a highly effective hybrid AI approach that integrates specialized tools for detection, image processing, text recognition, and contextual reasoning. By achieving robust and accurate fully automated netlist generation from schematic images, it provides a crucial tool for digitizing circuit knowledge, facilitating the creation of large-scale datasets for circuit AI, and enhancing EDA workflows. Its open-source nature further promotes reproducibility and future development in this field.