Reducing End-to-End Latency of Cause-Effect Chains with Shared Cache Analysis

Cause-effect chains, as a widely used modeling method in real-time embedded systems, are extensively applied in various safety-critical domains. End-to-end latency, as a key real-time attribute of cause-effect chains, is crucial in many applications. But the analysis of end-to-end latency for cause-effect chains on multicore platforms with shared caches still presents an unresolved issue. Traditional methods typically assume that the worst-case execution time (WCET) of each task in the cause-effect chain is known. However, in the absence of scheduling information, these methods often assume that all shared cache accesses result in misses, leading to an overestimation of WCET and, consequently, affecting the accuracy of end-to-end latency. However, effectively integrating scheduling information into the WCET analysis process of the chains may introduce two challenges: first, how to leverage the structural characteristics of the chains to optimize shared cache analysis, and second, how to improve analysis accuracy while avoiding state space explosion. To address these issues, this paper proposes a novel end-to-end latency analysis framework designed for multi-chain systems on multicore platforms with shared caches. This framework extracts scheduling information and structural characteristics of cause-effect chains, constructing fine-grained and scalable inter-core memory access contexts at the basic block level for time-sensitive shared cache analysis. This results in more accurate WCET (TSC-WCET) estimates, which are then used to derive the end-to-end latency. Finally, we conduct experiments on dual-core and quad-core systems with various cache configurations, which show that under certain settings, the average maximum end-to-end latency of cause-effect chains is reduced by up to 34% and 26%.

💡 Research Summary

The paper tackles the long‑standing problem of accurately estimating end‑to‑end latency for cause‑effect chains running on multicore platforms that share a common L2 cache. Traditional approaches assume that the worst‑case execution time (WCET) of each task is known a priori and, lacking concrete scheduling information, they conservatively treat every shared‑cache access as a miss. This leads to severe over‑pessimism that propagates to the end‑to‑end latency bound, making the analysis unusable for safety‑critical domains such as automotive electronics or industrial control.

To overcome this, the authors propose a novel analysis framework that tightly integrates scheduling information and the structural properties of cause‑effect chains into the shared‑cache analysis. The key ideas are:

1. Exploitation of Chain Structure – Cause‑effect chains are linear directed acyclic graphs with deterministic activation patterns (periodic for time‑triggered (TT) chains, immediate for event‑triggered (ET) chains). By focusing on ET chains and a special class of back‑to‑back TT chains, the framework can predict the exact release times of each task instance on each core.

2. Fine‑Grained Inter‑Core Context Modeling – Using control‑flow graphs (CFGs) and loop nesting information, the method constructs a “relative time” model for every basic block. Instead of treating the whole execution interval as a possible window for memory accesses (as done in coarse‑grained approaches), it approximates the execution window of each block relative to the system start time. This yields a lightweight yet precise context that captures when a block may issue a memory access.

3. Hierarchical Interference Identification – Interference is examined at three levels: (a) task‑instance level, (b) loop level, and (c) basic‑block level. At each level the framework checks for temporal overlap using the relative‑time contexts. If two blocks cannot overlap because of mutually exclusive loops or because they belong to different chains with non‑overlapping offsets, the corresponding interference is discarded. This “exclusion‑based reduction” dramatically shrinks the set of worst‑case interference scenarios.

4. Cache Hit/Miss Classification (CHMC) Refinement – A single‑core abstract‑interpretation analysis first classifies each memory access into Always‑Hit (AH), Always‑Miss (AM), Persistent (PS) or Not‑Classified (NC). For AH and PS accesses the maximum age under LRU replacement is computed. The inter‑core context is then used to decide whether other cores can evict the line, refining the CHMC and possibly converting an AH into a miss in the worst case.

5. Integration with Pipeline and ILP – The refined CHMC, together with pipeline stall models, yields a cost for each basic block. These costs are fed into an integer linear programming (ILP) formulation that computes the Time‑Sensitive Cache WCET (TSC‑WCET) for each task. Because the ILP respects the relative‑time constraints, the resulting WCET is both safe (never under‑estimates) and significantly tighter than conventional WCET.

6. End‑to‑End Latency Derivation – With TSC‑WCET values and the known schedule (release times, offsets, priorities), the framework computes the maximum end‑to‑end latency for each chain.

Experimental Evaluation
The authors implemented the approach and evaluated it on dual‑core and quad‑core platforms with a variety of L2 cache configurations (different sizes, associativities, line sizes). They compared against state‑of‑the‑art shared‑cache WCET analyses (e.g., Nagar’s ILP‑based method, Zhang’s happens‑before ordering) and against a baseline that assumes all shared accesses miss. Results show that the proposed method reduces the average maximum end‑to‑end latency by up to 34 % on dual‑core and 26 % on quad‑core systems. The improvement is most pronounced for caches with small line sizes and low associativity, where interference is more frequent.

Safety Proof
A formal proof is provided demonstrating that the relative‑time contexts over‑approximate all feasible execution orders, guaranteeing that the computed TSC‑WCET is an upper bound on the true worst‑case execution time. Consequently, the derived end‑to‑end latency bound is safe for real‑time certification.

Impact and Contributions
The paper makes four major contributions: (1) a complete end‑to‑end latency analysis framework that eliminates the pessimistic “all‑miss” assumption, (2) a scalable relative‑time context model at the basic‑block granularity, (3) a novel interference‑reduction mechanism that leverages intra‑ and inter‑program mutual exclusion, and (4) a safety proof ensuring the method’s applicability to safety‑critical certification processes. By tightly coupling scheduling knowledge with cache analysis, the work bridges a critical gap between WCET estimation and system‑level timing guarantees, offering a practical tool for designers of hard‑real‑time multicore systems.