LOCO: A Low-Cost SNU-Self-Resilient Latch Using an Output-Split C-Element

As the CMOS technology enters nanometer scales, integrated circuits (ICs) become increasingly sensitive to radiation-induced soft errors, which can corrupt the state of storage elements and cause severe reliability issues. Many hardened designs have been proposed to mitigate soft errors by using filtering elements. However, existing filtering elements only protect their inputs against soft errors and leave their outputs unprotected. Therefore, additional filtering elements must be added to protect outputs, resulting in extra overhead. In this paper, we first propose a novel Output-Split C-element (OSC) to protect both its input and output nodes, and then a novel LOw-COst single-node-upset (SNU) self-resilient latch (LOCO) to use OSCs to achieve both soft error resilience and low overhead. The usage of OSCs effectively reduce the short-circuit current of the LOCO latch during switching activities. Furthermore, the usage of clock gating and high-speed path reduces power consumption and delay, respectively. Compared with state-of-the-art SNU-resilient hardened designs, the LOCO latch achieves 19% fewer transistors, 63.58% lower power, 74% less delay, and 92% lower power-delay-product (PDP) on average. In addition, the LOCO latch exhibits better stability under variations in PVT (Process, Voltage, and Temperature).

💡 Research Summary

The paper addresses the growing vulnerability of nanometer‑scale CMOS circuits to radiation‑induced soft errors, focusing on single‑node upsets (SNUs) that can corrupt the state of storage elements such as latches. Existing hardened latch designs rely on filtering elements—dual‑input inverters, clock‑controlled inverters, conventional C‑elements, Schmitt‑Triggers, etc.—to block erroneous transients at the inputs. However, all of these elements leave their outputs unprotected, forcing designers to insert additional filters downstream. This cascade of filters inflates area, power, and delay, and still does not guarantee full self‑resilience because a corrupted output can feed back into the same element and become latched.

To overcome this fundamental limitation, the authors propose a novel Output‑Split C‑element (OSC). The OSC is a six‑transistor block with two inputs (I1, I2) and two physically separate outputs (O1, O2). When I1 = I2, the OSC behaves like an inverter; when the inputs differ, one output goes high‑impedance (retaining its previous value) while the other outputs the complement of I2. Crucially, the two outputs are coupled through two extra transistors (M4, M5) that automatically restore a corrupted output by pulling it back to the correct logic level. Thus, both inputs and both outputs are protected against SNUs, a capability that no existing filter element possesses.

Building on the OSC, the authors design the LOCO latch (Low‑Cost Self‑Resilient latch). LOCO consists of two OSCs, two transmission gates (TG0, TG1), a dual‑input inverter, and a clock‑controlled dual‑input inverter. In transparent mode (CLK = 1, CLKB = 0), TG0 and TG1 are ON, allowing the data input D to pass directly to the output Q while the clock‑controlled transistors are OFF to avoid current competition. In hold mode (CLK = 0, CLKB = 1), the transmission gates are OFF and the clock‑controlled transistors turn ON, forming two feedback loops through the OSCs. Each OSC’s internal recovery mechanism ensures that any SNU occurring on its inputs (nodes N0, Q, N5) or outputs (nodes N1‑N4) is automatically corrected. The paper presents two representative fault injection scenarios: (Case‑A) an SNU on node N0, and (Case‑B) an SNU on node N1. In both cases, the feedback paths and the restorative transistors quickly bring the faulty node back to its original state, eliminating short‑circuit conditions and preserving the correct output.

The authors evaluate LOCO using 22 nm PTM SPICE simulations with a double‑exponential current pulse model for SNU injection. Compared with state‑of‑the‑art SNU‑resilient hardened latches (e.g., STAHL, HLR, RFC, RFEL, HiPeR, HIDER, ISEHL), LOCO achieves on average:

• 19 % fewer transistors,
• 63.58 % lower static power,
• 74 % reduced propagation delay,
• 92 % lower power‑delay product (PDP).

The OSC’s design reduces short‑circuit current during switching, and the use of clock gating eliminates unnecessary leakage in transparent mode. A high‑speed transmission path further trims delay. Monte‑Carlo and PVT (process, voltage, temperature) corner simulations confirm that LOCO’s performance and resilience remain stable across a wide range of operating conditions.

In summary, the paper makes two key contributions: (1) the Output‑Split C‑element, the first filter that simultaneously protects both inputs and outputs from SNUs; (2) the LOCO latch, which leverages OSCs to achieve full self‑resilience with markedly lower area, power, and delay than existing designs. By eliminating the need for extra downstream filters, LOCO offers a compact, low‑power, high‑reliability solution suitable for safety‑critical applications such as autonomous vehicles, aerospace, and space electronics, where radiation tolerance and energy efficiency are paramount.