Enabling Technologies for Scalable Superconducting Quantum Computing

Experiments with superconducting quantum processors have successfully demonstrated the basic functions needed for quantum computation and evidence of utility, albeit without a sizable array of error-corrected qubits. The realization of the full potential of quantum computing centers on achieving large scale fault-tolerant quantum computers. Science, engineering and industry advances are needed to robustly generate, sustain, and efficiently manipulate an exponentially large computational (Hilbert) space as well as supply the number and quality components needed for such a scaled system. In this article, we suggest critical areas of quantum system and ecosystem development, with respect to the handling and transmission of quantum information within and out of a cryogenic environment, that would accelerate the development of quantum computers based on superconducting circuits.

💡 Research Summary

The paper provides a comprehensive roadmap for scaling superconducting quantum processors to the fault‑tolerant regime, focusing on the engineering challenges that arise when moving from tens of qubits to thousands or millions of physical qubits. The authors argue that a monolithic increase in chip size quickly runs into yield, frequency‑collision, and wiring‑complexity bottlenecks, and therefore propose a modular quantum processor (QPU) architecture. In this approach, small “chiplet” qubit dies are assembled on an interposer or connectorized package, and multiple such modules are stacked on a cryogenic back‑plane. Four categories of inter‑module links are identified based on distance and temperature: (a) on‑chip microwave transmission lines (sub‑centimeter), (b) short inter‑chip links (~1 cm), (c) medium‑length coaxial or waveguide cables (10 cm–1 m), and (d) long‑range connections (>1 km) that require microwave‑to‑optical transduction. Short links enable direct qubit‑qubit swaps with minimal loss, while longer links demand high‑Q cables, “bright‑mode” photon exchange, or conversion to itinerant optical photons. The authors discuss the trade‑offs between “dark‑mode” loss‑suppressed swaps (slower) and “bright‑mode” high‑speed swaps (requiring ultra‑low‑loss interconnects).

From the error‑correction perspective, modularity introduces new constraints on code distance and logical operation placement. The paper surveys both surface‑code and high‑density quantum LDPC (qLDPC) schemes, noting that inter‑module interconnects must preserve the same code distance as intra‑module couplers. This imposes stringent requirements on inter‑module fidelity, density, and latency, influencing hardware layout, compilation strategies, and decoder design. Reducing the number of modules (e.g., by increasing the logical‑to‑physical qubit ratio) can alleviate some of these pressures, and recent advances in qLDPC codes show promise for hardware‑friendly fault tolerance.

Cryogenic infrastructure is identified as the next major scaling bottleneck. Current commercial dilution refrigerators deliver roughly 20 µW of cooling power at 20 mK, sufficient for a few hundred qubits but far short of the megabit regime. The authors propose modular refrigerator architectures, where multiple fridge units are linked via thermal tunnels, allowing incremental capacity growth while keeping per‑qubit cooling cost roughly constant. They present a power budget (Table I) indicating that a 1 k‑qubit module would require ~1 mW of cooling per channel (3–4 channels per qubit) and ~30–40 W of cooling for the intermediate‑temperature (4–20 K) control electronics stage. Scaling to fault‑tolerant systems could push total wall‑plug power into the gigawatt range, comparable to modern data centers. Consequently, improvements in pulse‑tube efficiency, high‑temperature cryo‑CMOS, low‑noise amplifiers placed at higher stages, and alternative cooling technologies (e.g., liquid‑helium plants with higher Carnot efficiency) are essential for “green” quantum computing.

The paper also highlights the scarcity of ^3He, a critical resource for dilution refrigeration. Efficient use of ^3He volume per qubit becomes increasingly important as system size grows, motivating designs that keep qubits as close as possible to the base temperature while moving ancillary electronics to higher temperature stages.

In summary, the authors outline a four‑pillar strategy for scalable superconducting quantum computing: (1) modular QPU design with flexible microwave and optical interconnects, (2) robust error‑correction architectures that tolerate module boundaries, (3) modular, high‑efficiency cryogenic infrastructure with careful power budgeting, and (4) strategic allocation of scarce cryogenic resources. By quantifying the required temperatures, cooling powers, link lengths, and fidelity thresholds, the paper provides a concrete technical foundation for academia, industry, and government agencies to coordinate investments and research efforts toward building large‑scale, fault‑tolerant quantum computers.