Surrogate Neural Architecture Codesign Package (SNAC-Pack)

📝 Abstract

Neural Architecture Search is a powerful approach for automating model design, but existing methods struggle to accurately optimize for real hardware performance, often relying on proxy metrics such as bit operations. We present Surrogate Neural Architecture Codesign Package (SNAC-Pack), an integrated framework that automates the discovery and optimization of neural networks focusing on FPGA deployment. SNAC-Pack combines Neural Architecture Codesign’s multi-stage search capabilities with the Resource Utilization and Latency Estimator, enabling multi-objective optimization across accuracy, FPGA resource utilization, and latency without requiring time-intensive synthesis for each candidate model. We demonstrate SNAC-Pack on a high energy physics jet classification task, achieving 63.84% accuracy with resource estimation. When synthesized on a Xilinx Virtex UltraScale+ VU13P FPGA, the SNAC-Pack model matches baseline accuracy while maintaining comparable resource utilization to models optimized using traditional BOPs metrics. This work demonstrates the potential of hardware-aware neural architecture search for resource-constrained deployments and provides an open-source framework for automating the design of efficient FPGA-accelerated models.

💡 Analysis

Neural Architecture Search is a powerful approach for automating model design, but existing methods struggle to accurately optimize for real hardware performance, often relying on proxy metrics such as bit operations. We present Surrogate Neural Architecture Codesign Package (SNAC-Pack), an integrated framework that automates the discovery and optimization of neural networks focusing on FPGA deployment. SNAC-Pack combines Neural Architecture Codesign’s multi-stage search capabilities with the Resource Utilization and Latency Estimator, enabling multi-objective optimization across accuracy, FPGA resource utilization, and latency without requiring time-intensive synthesis for each candidate model. We demonstrate SNAC-Pack on a high energy physics jet classification task, achieving 63.84% accuracy with resource estimation. When synthesized on a Xilinx Virtex UltraScale+ VU13P FPGA, the SNAC-Pack model matches baseline accuracy while maintaining comparable resource utilization to models optimized using traditional BOPs metrics. This work demonstrates the potential of hardware-aware neural architecture search for resource-constrained deployments and provides an open-source framework for automating the design of efficient FPGA-accelerated models.

📄 Content

FERMILAB-CONF-25-0834-CSAID Surrogate Neural Architecture Codesign Package (SNAC-Pack) Jason Weitz University of California San Diego La Jolla, CA 92093, USA jdweitz@ucsd.edu Dmitri Demler University of California San Diego La Jolla, CA 92093, USA ddemler@ucsd.edu Benjamin Hawks Fermi National Accelerator Laboratory Batavia, IL 60510, USA bhawks@fnal.gov Nhan Tran Fermi National Accelerator Laboratory Batavia, IL 60510, USA ntran@fnal.gov Javier Duarte University of California San Diego La Jolla, CA 92093, USA jduarte@ucsd.edu Abstract Neural Architecture Search is a powerful approach for automating model design, but existing methods struggle to accurately optimize for real hardware performance, often relying on proxy metrics such as bit operations. We present Surrogate Neu- ral Architecture Codesign Package (SNAC-Pack), an integrated framework that automates the discovery and optimization of neural networks focusing on FPGA deployment. SNAC-Pack combines Neural Architecture Codesign’s multi-stage search capabilities with the Resource Utilization and Latency Estimator, enabling multi-objective optimization across accuracy, FPGA resource utilization, and la- tency without requiring time-intensive synthesis for each candidate model. We demonstrate SNAC-Pack on a high energy physics jet classification task, achieving 63.84% accuracy with resource estimation. When synthesized on a Xilinx Virtex UltraScale+ VU13P FPGA, the SNAC-Pack model matches baseline accuracy while maintaining comparable resource utilization to models optimized using tra- ditional BOPs metrics. This work demonstrates the potential of hardware-aware neural architecture search for resource-constrained deployments and provides an open-source framework for automating the design of efficient FPGA-accelerated models. 1 Introduction Machine learning models are applied across diverse domains, achieving state-of-the-art performance. Yet, deploying these models in resource-constrained environments, such as edge devices, is challeng- ing due to strict hardware and latency requirements. In order to meet these constraints, researchers have developed methods such as automated architecture design and model compression. Neural Architecture Search (NAS) can automate model design, but existing approaches typically optimize for accuracy alone or use simplistic computational metrics like bit operations (BOPs) that approximate actual hardware performance. Machine Learning and the Physical Sciences Workshop, NeurIPS 2025. arXiv:2512.15998v1 [cs.LG] 17 Dec 2025 To address this challenge, we introduce Surrogate Neural Architecture Codesign Package (SNAC- Pack), an integrated software framework that automates the discovery and optimization of neural network architectures specifically tailored for hardware deployment. SNAC-Pack combines two tools: Neural Architecture Codesign [1], which performs a multi-stage neural architecture search to discover optimal models, and the Resource Utilization and Latency Estimator [2], which uses a surrogate model to predict how an architecture will perform when synthesized for implementation on an FPGA. By integrating a fast and accurate surrogate model for resource estimation directly into the search stage, SNAC-Pack can perform a more effective multi-objective optimization for accuracy, hardware resource usage, and latency while avoiding time-intensive full hardware synthesis for every candidate model. This work explores the use of SNAC-Pack on a jet classification task [3], from a search space to a synthesized model. The SNAC-Pack software is available here. 2 Related Work Neural Architecture Search (NAS) [4, 5] is an automated process that explores a search space of model architectures with a search strategy based on a set of evaluation objectives, such as accuracy. Neural Architecture Codesign (NAC) [1] is a multi-stage NAS, consisting of a global and local search. The global search explores a wide range of architectures, resulting in a Pareto front of well-performing models. Selecting an architecture along this front, local search performs model compression, including quantization-aware-training (QAT) [6] and pruning [7]. With this further refinement, the model is then synthesized with hls4ml [8, 9]. Separately, surrogate models [10, 11] have been developed to accelerate the design cycle by providing rapid feedback on hardware performance without time-consuming synthesis runs. The rule4ml library [2], for instance, introduces a method to accurately predict the resource utilization, including block ram (BRAM), digital signal processors (DSPs), flip flops (FFs), lookup tables (LUTs), initiation interval (II), and latency of a neural network on an FPGA. 3 Method The SNAC-Pack tool builds upon NAC by introducing the additional objectives that can be estimated with rule4ml. With NAC integration, the global search stage begins with a user-defined search space that specifies the range of possible architectures, such as the types of

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