Deep Photonic Reservoir Computing with On-chip Nonlinearity

Reservoir computing, renowned for its low training cost, has emerged as a promising lightweight paradigm for efficient spatiotemporal processing,it remains challenging to realize deep photonic reservoir computing (DPRC) systems, due to the lack of scalable on-chip nonlinearity. Here, we introduce a versatile time delayed DPRC framework that natively supports deep and concurrent spatiotemporal processing entirely in the optical domain. At its core, the system leverages free carrier dynamics in silicon microring resonators to provide the fundamental nonlinearity and short term memory, and these nonlinear nodes are interconnected through true time delay lines that establish shared long-term memory. Benefiting from intrinsic physical nonlinearity and multi-timescale fading memory, this simple yet effective architecture demonstrates remarkable high dimensional representation capabilities. On the NTU RGB D benchmark, the parameter efficient DPRC system achieves superior action recognition accuracies compared to mainstream deep learning models, while requiring only a single shot regression training procedure. We further verify a prototype DPRC chip that excels across diverse dataset classification and time series prediction tasks. It enables a streamlined all optical pipeline between hierarchical layers, delivering a consistent computational density of 334.25 TOPs/mm2, independent of the reservoir depth and three orders of magnitude higher than conventional approaches. Moreover, its performance scales with near-zero hardware overhead by utilizing additional wavelength channels. This DPRC network is highly scalable on a silicon photonic platform, with flexible extension to hundreds of deep reservoir layers and parallel channels, paving the way toward intelligent optoelectronic systems for advanced real time processing and parallel decision making.

💡 Research Summary

The paper presents a novel deep photonic reservoir computing (DPRC) architecture that leverages intrinsic free‑carrier dynamics in silicon microring resonators (MRRs) to provide on‑chip nonlinearity and short‑term memory, while true time‑delay lines supply long‑term memory. By combining these two physical mechanisms, each MRR functions as a nonlinear node with multi‑timescale fading memory: fast carrier generation and dispersion create a nonlinear response on the picosecond photon‑lifetime scale, whereas carrier recombination (nanoseconds) introduces temporal coupling between successive virtual neurons. A single MRR can therefore host hundreds of virtual neurons through time‑multiplexing; the delay line closes the recurrent loop, giving the system a shared long‑term memory that spans several nanoseconds to tens of nanoseconds.

The architecture is hierarchical in two dimensions. The “depth” dimension is realized by stacking multiple reservoir layers, each implemented on a distinct wavelength channel. Wavelength‑division multiplexing (WDM) allows many parallel channels to share the same physical delay line, so adding layers incurs virtually no additional footprint or power. The “width” dimension is the number of virtual neurons per layer, controlled by the time‑division multiplexing factor. This dual scaling enables the construction of hundreds of deep layers and dozens of parallel channels on a compact silicon photonic chip.

To demonstrate the computational power of the system, the authors apply it to skeleton‑based human action recognition on the NTU‑RGB+D benchmark. Raw 3‑D joint data are normalized, temporally aligned, and grouped into five anatomical parts. Each part is reshaped into a 3 × D feature map and projected onto 15 input channels via a random mask. The 15 channels are fed sequentially into an L‑layer DPRC (L = 1…8) with 150 virtual neurons per layer. After a single forward pass, the states from all layers and channels are concatenated and a readout weight matrix is trained using ridge regression (regularization = 1e‑5). Accuracy improves monotonically with depth, reaching 98.1 % (cross‑view) and 96.7 % (cross‑subject) for an 8‑layer network. This performance surpasses state‑of‑the‑art graph convolutional networks and transformer models, despite using only ~1.1 M trainable parameters (≈150 × 8 × 15 × 60).

A series of ablation studies clarify the role of the physical mechanisms. Reducing the on‑chip pump power weakens the free‑carrier nonlinearity, causing a steep drop in accuracy; at 0.5 mW the 8‑layer system performs worse than a single‑layer system driven at 6 mW. Increasing pump power beyond 8 mW drives the MRR into a self‑pulsation regime where thermal effects dominate, again degrading performance. Varying the number of virtual neurons shows diminishing returns beyond ~150 neurons per layer, especially for deeper networks.

The hardware prototype is fabricated in a commercial silicon photonic foundry. The packaged chip (1.78 mm²) integrates six MRR channels, two spiral waveguide delay units, and three Mach‑Zehnder interferometer switches. Time‑domain measurements confirm the presence of two distinct output pulses separated by ~1.45 ns, evidencing the fading‑memory effect of the delay line. Nonlinear transient response is demonstrated by injecting a 20 Gbps sequence into an MRR pumped at 6 dBm with a 50 pm wavelength detuning, producing clear amplitude modulation at the output. The measured computational density reaches 334 TOPS mm⁻², three orders of magnitude higher than previous photonic reservoir implementations, and remains constant regardless of reservoir depth.

Overall, the work delivers four key contributions: (1) a scalable on‑chip nonlinear node based on free‑carrier effects, (2) a true time‑delay architecture that provides multi‑timescale memory, (3) wavelength‑multiplexed parallelism that scales depth without extra hardware, and (4) a single‑shot regression training pipeline that eliminates iterative back‑propagation. The resulting DPRC system offers ultrafast, energy‑efficient processing suitable for real‑time video analytics, robotic control, and high‑speed communications, and it paves the way toward large‑scale, fully optical neuromorphic processors.