AC-LGADs Fermilab Front-End Electronics Characterization

We characterized the front-end electronics used to process high-frequency signals from low-gain avalanche diodes (LGADs) at the Fermilab Test Beam Facility. LGADs are silicon detectors employed for charged particle tracking, offering exceptional spatial and temporal resolution. The purpose of this characterization was to understand how the time resolution is influenced by the front-end electronics. To achieve this, we developed a setup capable of generating input signals with varying amplitudes. The output results demonstrated that signal processing by the front-end electronics plays a crucial role in enhancing time resolution. We showed that the time resolution achieved by the FEE board is better than $2: ps$ at the $1σ$ level.

💡 Research Summary

The paper presents a comprehensive characterization of a 16‑channel front‑end electronics (FEE) board developed to read out AC‑coupled Low‑Gain Avalanche Diodes (AC‑LGADs) at the Fermilab Test Beam Facility. AC‑LGADs are silicon sensors that provide excellent spatial (≈6–10 µm) and temporal (≈30 ps) resolution, making them attractive for the high‑luminosity LHC upgrades where hundreds of simultaneous collisions must be disentangled. To exploit the intrinsic sensor performance, a dedicated read‑out chain is required; the authors therefore focus on the electrical behavior of the FEE board, which serves as the Device Under Test (DUT).

Each channel of the board incorporates a two‑stage amplifier based on the Minicircuits Gali S66+ monolithic microwave integrated circuit. The first stage presents a 25 Ω input impedance, the second stage is matched to 50 Ω, and the combined bandwidth spans DC to roughly 3 GHz. At 2 GHz the nominal gain is about 18 dB (≈66× voltage gain). The total trans‑impedance after both stages is ≈4.3 kΩ, and the conversion factor is 5 mV per femtocoulomb of input charge (100 mV output for a typical 20 fC MIP signal). The gain uniformity across the 16 channels varies by only ~10 %.

The experimental setup was carefully controlled: the board was powered at 6.8 V (0.537 A) and kept at 21.7 °C inside an EMI‑shielded enclosure. A low‑jitter (≤175 fs RMS) clock generator operating at 84.3 MHz supplied the timing reference. A custom pulse generator, built around the NB6L295 dual‑delay chip and an LVPECL AND gate, produced nanosecond‑wide pulses that emulate the charge deposition of a minimum ionizing particle. Variable attenuators allowed the input pulse amplitude to be swept from 0.94 mV to 5.19 mV, covering the range relevant for a 50 µm thick AC‑LGAD (≈20 fC charge). The pulses were injected via a specially designed charge‑injector board that provides 50 Ω matching, AC‑coupling, and a 100 nF series capacitor to remove common‑mode voltage.

Signal acquisition was performed with a LeCroy WaveRunner 610Zi oscilloscope (1 GHz bandwidth, 20 GS/s). The oscilloscope’s intrinsic 10‑90 % rise time of 375 ps sets the ultimate limit on measured rise times, which were observed around 350 ps—indicating that the board’s intrinsic response is faster than the measurement system can resolve.

Gain was quantified by directly measuring input and output pulse amplitudes for several attenuation settings. For a 56 dB attenuation the board delivered a voltage gain of 75 dB (≈5 × 10³), while at 40 dB attenuation the gain was 36 dB (≈4 × 10³). At the highest input amplitudes a modest gain compression was observed, consistent with the specifications of the Gali S66+.

Time resolution (jitter) was evaluated using the CMS‑MTD Timing DAQ framework. The reference clock and the amplified DUT signal were both recorded; the time difference at the 50 % rising‑edge crossing was computed for many events. The intrinsic jitter of the measurement chain (clock, pulse generator, oscilloscope, cabling) was measured separately by feeding the same pulse into a 50 Ω splitter and recording the two outputs, yielding σ_pulse‑generator = 4.13 ± 0.12 ps. When the FEE board was included, the jitter decreased with increasing signal‑to‑noise ratio (SNR) according to the model σ_t ≈ (Rise Time)/SNR + δ_t. The noise RMS remained roughly constant (≈1.8–2.9 mV) across the amplitude range, so the improvement in timing is driven primarily by the rise in signal amplitude. The data follow a quadratic sum of an SNR‑dependent term and a constant floor; the fitted asymptotic jitter (δ_t) is about 2 ps, confirming that the board itself contributes less than 2 ps to the overall timing budget at high SNR (≈70 dB).

In summary, the characterized FEE board provides:

• Uniform gain (~66×) across 16 channels with ≤10 % variation.
• Bandwidth sufficient to preserve sub‑nanosecond pulse edges (measured rise time ≈350 ps, limited by the oscilloscope).
• Stable noise performance (≈2 mV RMS) independent of signal amplitude.
• Time resolution better than 2 ps (1 σ) when the input signal corresponds to a typical MIP charge, thanks to the high SNR achieved after amplification.

These results demonstrate that the board meets the stringent timing requirements for AC‑LGAD‑based 4‑dimensional tracking detectors envisioned for the HL‑LHC and similar high‑luminosity experiments. The authors note that the measured rise times are limited by the oscilloscope, implying that the intrinsic performance of the board could be even better when paired with faster digitizers.