Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity
📝 Abstract
The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conventional input/output (I/O) circuitry, including electrostatic discharge (ESD) protection and signaling, introduces significant area overhead. Prior studies have identified this overhead as a major constraint in reducing chiplet size below 100 mm2. In this study, we revisit reliability requirements from the perspective of chiplet interface design. Through parasitic extraction and simulation program with integrated circuit emphasis (SPICE) simulations, we demonstrate that ESD protection and inter-chiplet signaling can be substantially simplified in future 2.5D/3D packaging technologies. Such simplification, in turn, paves the road for further chiplet miniaturization and improves the composability and reusability of tiny chiplets.
💡 Analysis
The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conventional input/output (I/O) circuitry, including electrostatic discharge (ESD) protection and signaling, introduces significant area overhead. Prior studies have identified this overhead as a major constraint in reducing chiplet size below 100 mm2. In this study, we revisit reliability requirements from the perspective of chiplet interface design. Through parasitic extraction and simulation program with integrated circuit emphasis (SPICE) simulations, we demonstrate that ESD protection and inter-chiplet signaling can be substantially simplified in future 2.5D/3D packaging technologies. Such simplification, in turn, paves the road for further chiplet miniaturization and improves the composability and reusability of tiny chiplets.
📄 Content
Heterogeneous integration (HI) systems, which leverage 2.5D and 3D packaging technologies to integrate multiple chiplets on an advanced packaging substrate, have emerged as a key enabler in modern very large-scale integration (VLSI) design [1,2]. These systems offer high flexibility, scalability, and high energy efficiency, particularly for data-intensive workloads such as high-performance computing, autonomous vehicles and AI tasks. By disaggregating a large monolithic design into smaller chiplets and interconnecting them through 2.5D and 3D integration, these systems effectively reduce design and fabrication costs, improve overall yield, provide higher bandwidth and lower energy consumption in data movement, and achieve better system reconfigurability [3,4].
However, previous studies have identified the I/O interface of chiplets, such as electrostatic discharge (ESD) protection, clock and data synchronization, and related area cost as a key limitation in scaling chiplet sizes below 100 mm 2 [5]. For instance, an implementation of the Advanced Interface Bus (AIB) [6], a widely adopted I/O module for 2.5D integration, occupies several mm 2 at 22nm, larger than many design IP blocks (such as CPUs, DSPs, FFT accelerators, and systolic arrays) [7]. These overheads restrict the reusability and composability of chiplets in heterogeneous integration [7].
In this study, we revisit the reliability requirements of chiplet interfaces, with a focus on advanced packaging technologies. As packaging continues to scale, with finer pitch, shorter inter-chiplet spacing, and lower electrical parasitics, we explore how these advancements can significantly reduce the overhead of ESD protection and inter-chiplet signaling, thereby eliminating conventional I/O bottlenecks and enabling future scaling of chiplet sizes (i.e., tiny chiplets).
A heterogeneous system typically comprises three primary components [1,2]: the chiplets, which serve as the functional units for computing, memory, control and other tasks; the interconnects, either horizontal or vertical, that connect the chiplets together to form a complete system; and the substrate, which can be silicon-, organic-or glass-based, providing the foundation for hosting both the interconnects and chiplets. Figure 1 illustrates such a heterogeneous system with multiple stacks of 2.5D and 3D chiplets on a common substrate, highlighting key features and parameters of wires between chiplets. Figure 2 presents a more detailed view of an individual 2.5D chiplet, with µbump arrays on each side for delivering signals, clocks, and power supply.
As packaging technologies advance, several physical features of HI systems continue to scale down. Table I outlines important geometric parameters related to the chiplet size and interconnect dimensions. Based on HI roadmaps [1,2], Tables II and III summarize the scaling trends of µbumps and hybrid bonds. These two structures form the critical interface between chiplets and the substrate or between chiplets
One of the key cost factors in chiplet-based design is electrostatic discharge protection for the I/O interface [5,8]. ESD poses a critical concern for the reliability of on-chip transistors, and its adverse impact becomes even more pronounced as complementary metal oxide semiconductor (CMOS) technology continues to scale. At the chiplet level, only the interfaces, such as µbumps and hybrid bonds, are exposed to potential ESD from the external environment and therefore, require protection.
ESD protection typically involves large diodes within I/O cells that clamp the ESD voltage below the damage threshold. However, this approach inevitably introduces significant area overhead and additional capacitive load on the signal channel, thereby limiting the usable chip area and reducing the data rate of inter-chiplet communication. Given the controlled clean room environment in advanced packaging, the JEDEC roadmap recommends reducing ESD protection targets from 250V today to 125V for scaled packaging technologies, and even down to as low as 5V for chiplet I/Os using hybrid bonding in 2.5D/3D systems [8].
To meet the JEDEC requirements of ESD protection, it is essential to determine the minimum diode size, which is affected by many factors, such as the parasitic resistance (R), inductance (L), and capacitance (C) along the I/O path. In this study, we use the circuit schematic for ESD validation, as shown in Fig. 3 [9,10]. We perform SPICE simulations to evaluate the diode size needed for ESD protection under the Charged Device Model (CDM) across generations. This generic schematic includes both the interconnect component and the pad structure, such as µbumps and hybrid bonds used in 2.5D/3D integration. Based on the dimensions listed in Table II, we adopt compact models to calculate the corresponding RLC parameters for each generation [11]. As an example, Table IV summarizes the parameters for µbumps. 4 presents the gate voltage waveforms at th
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