Resource-Efficient Cross-Platform Verification with Modular Superconducting Devices

Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state – a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two three-qubit modules on a single carrier chip, with connectivity for intra- and inter-module entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an inter-module two-qubit gate enables sub-exponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of four for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.

💡 Research Summary

The paper addresses a critical challenge for large‑scale quantum computing: how to efficiently verify that separate modules of a modular quantum processor prepare the same quantum state. Traditional cross‑platform verification relies solely on local operations and classical communication (LOCC) between modules. While LOCC can be efficient for low‑magic, low‑entanglement states, it scales exponentially with the number of qubits for arbitrary mixed states, quickly becoming impractical as systems grow.

To overcome this limitation, the authors introduce a modest quantum link between modules—a two‑qubit gate that directly couples a qubit in one module to a qubit in the other. This enables sample‑efficient protocols such as the SWAP test or Bell‑basis measurements, which dramatically reduce the number of repetitions required to estimate the inner product tr(ρ_A ρ_B) of the two states.

Experimentally, the team fabricates a six‑qubit flip‑chip superconducting device comprising two three‑qubit modules on a common carrier chip. Each module contains flux‑tunable transmons coupled in a two‑by‑three ladder topology, with both intra‑module and inter‑module two‑qubit gates realized via fast frequency tuning. Measured performance includes a median single‑qubit error of 0.11 % and a median two‑qubit error of 1.45 %, comparable to state‑of‑the‑art 3D‑integrated devices. Readout assignment errors are around 1 % for the computational basis and 2 % for the second‑excited (qutrit) level.

The verification protocol proceeds as follows. Both modules prepare an n‑qubit GHZ state |GHZ⟩(φ) = (|0⟩^{⊗n}+e^{iφ}|1⟩^{⊗n})/√2, with φ set to 0 on the left module and varied from 0 to 2π on the right. Quantum state tomography (QST) on each module yields density matrices ρ_A(φ=0) and ρ_B(φ). The inner product tr(ρ_A ρ_B) is then computed and compared to the theoretical (1+cos φ)/2. The QST results match theory closely, showing near‑unity overlap for identical states and near‑zero for orthogonal phases, though fidelity degrades with increasing n due to gate errors and leakage.

Next, the authors implement a Bell‑basis measurement (BBM) protocol that uses the inter‑module two‑qubit gate to entangle each pair of corresponding qubits in the Bell basis. After measurement, two n‑bit strings a_i and b_i are obtained; their bitwise AND parity π_k determines the inner product via tr(ρ_A ρ_B)=1−2π_k. BBM reproduces the same φ‑dependence but exhibits larger deviations because of the extra two‑qubit gates and readout misclassifications. Readout‑error mitigation reduces the maximum deviation from 0.25 to 0.17 for three‑qubit states.

A key quantitative finding is the resource scaling. To achieve a statistical variance of 10⁻³ in estimating the inner product of two identical three‑qubit GHZ states, the LOCC‑only QST approach requires roughly 2 000 measurement repetitions, whereas the BBM protocol with the quantum link needs only about 500 repetitions—a four‑fold reduction. The authors’ error model predicts that this advantage grows with system size: LOCC scales exponentially, while protocols that exploit even a single inter‑module entangling gate scale sub‑exponentially (effectively polynomial for realistic error rates).

In summary, the work demonstrates that modest quantum connectivity between modules can transform cross‑platform verification from an infeasible, exponentially costly task into a practical, resource‑efficient procedure. The six‑qubit flip‑chip device serves as a testbed, showing that with current superconducting technology, inner‑product estimation can be performed with high accuracy using either full tomography or Bell‑basis measurements. The results provide a concrete benchmark for future modular quantum processors, indicating that as the number of qubits per module increases, incorporating inter‑module entangling gates will be essential for scalable verification and, by extension, for reliable modular quantum computation.