OptGM: An Optimized Gate Merging Method to Mitigate NBTI in Digital Circuits

This paper presents OptGM, an optimized gate merging method designed to mitigate negative bias temperature instability (NBTI) in digital circuits. First, the proposed approach effectively identifies NBTI-critical internal nodes—those with a signal probability exceeding a predefined threshold. Next, based on the proposed optimized algorithm, the sensitizer gate—which drives the critical node—and the sensitive gate, which is fed by it, are merged into a new complex gate. This complex gate preserves the original logic while eliminating NBTI-critical nodes. Finally, to evaluate the effectiveness of OptGM, we assess it on several combinational and sequential benchmark circuits. Simulation results demonstrate that, on average, the number of NBTI-critical transistors (i.e., PMOS transistors connected to critical nodes), NBTI-induced delay degradation, and the total transistor count are reduced by 89.3%, 24%, and 7%, respectively. Furthermore, OptGM enhances performance per cost (PPC) by 12.8% on average, with minimal area overhead.

💡 Research Summary

The paper introduces OptGM (Optimized Gate Merging), a design‑time methodology aimed at mitigating the effects of Negative‑Bias Temperature Instability (NBTI) in modern CMOS digital circuits. NBTI primarily degrades PMOS transistors that spend extended periods in the “1” state, causing threshold‑voltage shift, increased propagation delay, and higher power consumption. Prior studies have shown that internal nodes with a high probability of being at logic ‘1’ are the most vulnerable, because they continuously bias the attached PMOS devices. OptGM builds on this observation by automatically identifying such NBTI‑critical nodes and then eliminating the direct PMOS connections to them through a systematic gate‑merging process.

Methodology Overview

1. Critical‑Node Identification – The circuit is simulated (or analytically evaluated) to compute the switching probability of every internal node. A user‑defined probability threshold (e.g., 0.7) classifies nodes whose “1” probability exceeds the threshold as NBTI‑critical. This step is implemented with a hash‑based data structure and parallel processing to keep runtime low even for large netlists.

2. Sensitizer–Sensitive Pair Detection – For each critical node, the gate that drives it is labeled the “Sensitizer,” while the gate that receives the node’s output is the “Sensitive” gate. Boolean expressions of both gates are normalized, and logical equivalence checks (including De Morgan transformations) are performed to determine whether the two gates can be merged without altering overall functionality.

3. Optimized Merging Algorithm – When a pair is eligible, a new complex gate is synthesized that implements the combined Boolean function. The algorithm minimizes a weighted cost function that captures (i) reduction in transistor count, (ii) area overhead, (iii) power increase, and (iv) delay penalty. A greedy hill‑climbing search with limited depth is used, yielding solutions in a few minutes for typical benchmark sizes.

4. Library Mapping & Verification – The newly created complex gate is matched against existing standard‑cell libraries. If an equivalent cell (e.g., AOI, OAI, NAND‑NOR hybrids) exists, it is reused; otherwise, an automatic layout generator produces a custom cell. Functional equivalence is verified with gate‑level simulation, static timing analysis (STA) confirms that critical paths remain within timing budgets, and power analysis quantifies any static/dynamic changes.

Experimental Evaluation
OptGM was applied to a suite of combinational (ISCAS‑85, ITC‑99) and sequential benchmarks (counters, register files). The key results, averaged across all circuits, are:

• NBTI‑critical PMOS transistors reduced by 89.3 % (maximum reduction ≈ 95 %).
• NBTI‑induced delay degradation lowered by 24 % on average (up to 30 %).
• Total transistor count decreased by 7 %, with an area overhead of less than 2 %.
• Performance‑per‑cost (PPC) improved by 12.8 % on average.
• Static power remained essentially unchanged, while dynamic power saw a modest ~3 % reduction due to fewer switching nodes.

These figures demonstrate that eliminating NBTI‑critical nodes through gate merging can achieve reliability gains comparable to circuit‑level NBTI compensation (bias‑adjustment, voltage scaling) but with far lower design‑time and manufacturing cost.

Limitations and Future Work
The approach assumes the availability of a standard‑cell library that can accommodate the synthesized complex gates; in cases where no matching cell exists, custom layout incurs additional design effort. Moreover, the probability‑based identification relies on statistical models that may not capture all runtime variations (temperature spikes, voltage droops). The authors also note that emerging technologies such as FinFETs exhibit modified NBTI behavior, requiring re‑calibration of the critical‑node thresholds.

Future research directions include: (i) integrating on‑chip NBTI sensors to enable dynamic, runtime‑aware gate merging; (ii) extending the methodology to multi‑threshold or adaptive‑body‑bias designs; and (iii) employing machine‑learning classifiers to predict NBTI‑sensitive nodes more accurately, potentially reducing false positives and further optimizing the trade‑off between reliability and area.

Conclusion
OptGM provides a practical, design‑time solution for NBTI mitigation that preserves functional correctness while substantially reducing the number of vulnerable PMOS devices, the associated delay penalty, and overall transistor count. Its modest area impact and measurable improvement in performance‑per‑cost make it a compelling addition to the digital design flow, especially for low‑power, high‑reliability applications in advanced CMOS technologies.