Implementation of Quantum Fourier Transform and Quantum Hashing for a Quantum Device with Arbitrary Qubits Connection Graphs

In the paper, we consider quantum circuits for Quantum fingerprinting (quantum hashing) and quantum Fourier transform (QFT) algorithms. Quantum fingerprinting (quantum hashing) is a well-known technique for comparing large objects using small images. The QFT algorithm is a very popular technique used in many algorithms. We present a generic method for constructing quantum circuits for these algorithms for quantum devices with restrictions. Many quantum devices (for example, based on superconductors) have restrictions on applying two-qubit gates. The restrictions are presented by a qubits connection graph. Typically, researchers consider only the linear nearest neighbor (LNN) architecture, but current devices have more complex graphs. We present a method for arbitrary connected graphs that minimizes the number of CNOT gates in the circuit. The heuristic version of the method is fast enough and works with $O(n^5)$ time complexity, where $n$ is the number of qubits. The certain version of the algorithm has an exponential time complexity that is $O(n^22^n)$. We compare quantum circuits built by our algorithm with quantum circuits optimized for specific graphs that are Linear-nearest-neighbor (LNN) architecture, sun'' (a cycle with tails, presented by 16-qubit IBMQ device) and two joint suns’’ (two joint cycles with tails, presented by 27-qubit IBMQ device). Our generic method gives similar results with little bit more CNOT gates. At the same time, our method allows us to construct a circuit for arbitrary connected graphs.

💡 Research Summary

The paper addresses the practical problem of implementing quantum Fourier transform (QFT) and quantum fingerprinting (quantum hashing) circuits on near‑term quantum devices that have restricted two‑qubit connectivity. The authors model the physical connectivity of a device as an undirected graph G(V,E), where vertices represent qubits and edges indicate where a CNOT gate can be directly applied. While most prior work focuses on the linear‑nearest‑neighbor (LNN) architecture, real superconducting devices such as IBM’s Eagle r3 chips exhibit more complex topologies (e.g., “sun” and “two‑joint‑sun” graphs).

The core contribution is a generic method that, for any connected graph, constructs a circuit with a near‑optimal number of CNOT gates. The method proceeds by converting the connectivity problem into a variant of the traveling salesman problem (TSP). First, a complete weighted graph S is built where the weight of an edge (u′,v′) equals the shortest‑path distance between the corresponding qubits u and v in G. Solving the TSP on S yields an ordering of vertices that minimizes the total distance. Mapping this ordering back to G by concatenating the shortest paths between consecutive vertices produces a non‑simple walk that visits every qubit at least once. Lemma 1 and Lemma 2 prove that this walk is the shortest possible under the given constraints.

Two algorithmic variants are presented. The exact version employs the Bellman‑Held‑Karp dynamic programming algorithm, achieving optimal TSP solutions in O(n² 2ⁿ) time, where n is the number of qubits. Because this is exponential, a heuristic version with O(n⁵) time complexity is also provided; it guarantees a 2‑approximation of the optimal TSP length. Both versions output an ordering that can be directly translated into a sequence of CNOTs respecting the device’s connectivity.

Applying the method to QFT, the authors derive CNOT counts that range from 1.5 n² – 1.5 n – 1 (when the graph contains a Hamiltonian path) up to 1.5 n³ – 1.5 n² – 2 n for highly irregular graphs. For the specific IBM architectures examined—16‑qubit “sun” and 27‑qubit “two‑joint‑sun”—the generic method yields 342 and 1 009 CNOTs respectively, compared with 324 and 957 CNOTs from hand‑crafted, architecture‑specific designs, i.e., roughly a 5 % overhead.

Quantum hashing circuits share a structural similarity with QFT, relying on uniformly controlled rotation gates. By reusing the same graph‑to‑TSP mapping, the authors obtain CNOT counts of 3 n – 2 in the best case (Hamiltonian path) and up to 1.5 n² + 1.5 n – 2 in the worst case. For ℓ repetitions of the hashing protocol, the total CNOT cost scales linearly with ℓ, preserving the same asymptotic bounds. When applied to LNN and the aforementioned IBM graphs, the generic method matches the CNOT counts of specialized circuits, confirming its versatility.

Experimental evaluation on real IBMQ devices demonstrates that the heuristic algorithm runs orders of magnitude faster than the exact O(n² 2ⁿ) version while still producing circuits with only a modest CNOT increase. The authors also discuss the trade‑off between circuit depth and CNOT count, noting that their approach can be combined with existing gate‑level optimizers for further reductions.

In summary, the paper introduces a unified, graph‑theoretic framework that transforms connectivity‑constrained quantum circuit synthesis into a TSP problem, provides both exact and practical heuristic solutions, and validates the approach on state‑of‑the‑art superconducting hardware. This work bridges the gap between theoretical algorithm design and hardware‑aware implementation, offering a scalable pathway for deploying QFT and quantum hashing on arbitrary quantum processor topologies.