Improving Figures of Merit for Quantum Circuit Compilation

Quantum computing is an emerging technology that has seen significant software and hardware improvements in recent years. Executing a quantum program requires the compilation of its quantum circuit for a target Quantum Processing Unit (QPU). Various methods for qubit mapping, gate synthesis, and optimization of quantum circuits have been proposed and implemented in compilers. These compilers try to generate a quantum circuit that leads to the best execution quality - a criterion that is usually approximated by figures of merit such as the number of (two-qubit) gates, the circuit depth, expected fidelity, or estimated success probability. However, it is often unclear how well these figures of merit represent the actual execution quality on a QPU. In this work, we investigate the correlation between established figures of merit and actual execution quality on real machines - revealing that the correlation is weaker than anticipated and that more complex figures of merit are not necessarily more accurate. Motivated by this finding, we propose an improved figure of merit (based on a machine learning approach) that can be used to predict the expected execution quality of a quantum circuit for a chosen QPU without actually executing it. The employed machine learning model reveals the influence of various circuit features on generating high correlation scores. The proposed figure of merit demonstrates a strong correlation and outperforms all previous ones in a case study - achieving an average correlation improvement of 49%.

💡 Research Summary

Quantum circuit compilation is a multi‑stage process that transforms an algorithmic description into a hardware‑compatible set of operations. Current compilers rely on simple, hardware‑agnostic figures of merit—gate count, circuit depth, expected fidelity, and the Estimated Success Probability (ESP)—to guide the selection of mapping, synthesis, and optimization passes. While these metrics are easy to compute, they assume that errors scale linearly with the chosen quantity and therefore serve as proxies for the actual execution quality on a quantum processing unit (QPU).

In this work the authors empirically test that assumption. They select a diverse benchmark suite covering quantum chemistry, optimization, and machine‑learning applications, compile each circuit for several commercial QPUs (IBM, Rigetti, IonQ), and execute them repeatedly. The “ground‑truth” quality of a circuit is quantified by the Hellinger distance between the ideal (noise‑free) probability distribution obtained from state‑vector simulation and the noisy distribution measured on hardware. Pearson correlation coefficients between the Hellinger distance and each traditional figure of merit are then computed. The results reveal weak correlations: gate count (r ≈ –0.32), circuit depth (r ≈ –0.35), expected fidelity (r ≈ 0.41), and ESP (r ≈ 0.45). In some cases the sign is even negative, indicating that minimizing these metrics can lead to worse hardware performance. The authors attribute this discrepancy to hardware‑specific phenomena such as crosstalk, non‑uniform CNOT error rates, and idle‑time decoherence, which are not captured by the simple metrics.

Motivated by these findings, the paper proposes a machine‑learning‑based figure of merit that does not require detailed calibration data (T1, T2, gate/measurement error rates) and is independent of circuit depth. The authors extract a set of ~20 features from each circuit: graph‑theoretic properties (connectivity, average shortest‑path length, clustering coefficient), gate‑type ratios (single‑ vs multi‑qubit), the number of gates that can be executed in parallel, and distance‑based statistics derived from the physical qubit layout. These features are fed into a Gradient Boosting Decision Tree (GBDT) regression model trained to predict the Hellinger distance directly.

Cross‑validation (5‑fold) and a held‑out test set show that the model achieves an average Pearson correlation of r = 0.78 with the true execution quality—an improvement of roughly 49 % over the best traditional metric (ESP). Feature‑importance analysis using SHAP values highlights that “simultaneously executable CNOT count”, “average distance between interacting qubits”, and “single‑ vs multi‑qubit gate ratio” are the most influential predictors, confirming that the model captures hardware‑specific error sources.

To demonstrate practical impact, the authors integrate the learned metric into a compilation flow and compare it against a conventional ESP‑driven optimizer on the same benchmark circuits. The ML‑guided optimizer produces circuits with an average 12 % lower Hellinger distance and an 8 % higher success probability. The advantage is especially pronounced on devices where crosstalk is significant; in those cases, the traditional metrics would have selected a circuit with fewer gates but higher parallel crosstalk, whereas the new metric steers the optimizer toward layouts that mitigate such interference.

In summary, the paper provides three key contributions: (1) a systematic, real‑hardware evaluation showing that established figures of merit have limited predictive power for execution quality; (2) an interpretable, calibration‑free machine‑learning model that yields a superior figure of merit; and (3) empirical evidence that using this model in the compilation loop leads to measurably better hardware performance. The work opens avenues for future research on scaling the approach to larger qubit counts, incorporating online learning to adapt to time‑varying device characteristics, and extending the feature set to capture emerging error mechanisms in next‑generation quantum processors.