Experimental timing and control using microcontrollers

Modern physics experiments rely on precise timing provided by programmable digital pulse generators. In many experimental control systems, this role is filled by custom devices built on Field Programmable Gate Arrays (FPGAs). While highly flexible and performant, these systems can be difficult to scale to very large systems due to cost and complexity. Recent advances in microcontroller systems allows these much simpler systems to fill the role of digital pulse generators. Here we demonstrate one such alternative based on the Raspberry Pi Pico microcontroller which allows for timing resolution down to 7.5 ns with a minimum pulse width of of 37.5 ns.

💡 Research Summary

The paper presents a low‑cost, high‑performance digital pulse‑generation platform built around the Raspberry Pi Pico (RP2040) microcontroller, offering timing resolution down to 7.5 ns and a minimum pulse width of 37.5 ns. Recognizing that many modern physics experiments still rely on FPGA‑based pulse generators for precise, repeatable timing, the authors argue that the expense, power consumption, and programming complexity of FPGAs become prohibitive as experiments scale up, especially in quantum‑information and AMO (atomic, molecular, optical) research.

The RP2040’s architecture provides the necessary hardware primitives: a 133 MHz system clock (yielding 7.5 ns per clock cycle), dual‑core Cortex‑M0+ CPUs, four Programmable I/O (PIO) blocks each with four independent state machines, a DMA controller, and 264 kB of SRAM. By off‑loading real‑time GPIO toggling to the PIO state machines and feeding them with pre‑loaded instruction streams via DMA, the system can generate deterministic edges at the granularity of a single clock cycle without CPU intervention.

Two complementary firmware packages are introduced:

1. Prawn blaster – Implements “pseudo‑clock” outputs. Each pseudo‑clock is defined by two 32‑bit words: a half‑period (number of clock cycles the line stays high, then low) and a repetition count. This compact representation allows complex multi‑rate sequences (e.g., five short‑period pulses, one long‑period pulse, three intermediate‑period pulses) to be described with only three commands. Such clock‑like triggers are ideal for driving ADC/DAC sampling clocks, where many identical triggers are required but the duty cycle must remain 50 %.

2. PrawnDO – Generates fully arbitrary pulse patterns. Instructions use run‑length encoding: each entry specifies the output state (high/low) and the duration (in clock cycles). The example waveform in the paper requires seven instructions, one per edge. This mode supports non‑symmetrical duty cycles, gating, and single‑event triggers (e.g., oscilloscope captures).

The system communicates with a host PC over USB Full‑Speed (12 Mbit/s) using a CDC (serial) interface. Human‑readable ASCII commands handle configuration, while bulk binary transfers load the instruction buffer at up to 650 kbit/s, filling the entire SRAM (≈30 000 instructions) in ~270 ms. The host can start, stop, or abort execution, and can poll status until completion.

Performance metrics: with a 100 MHz clock the timing granularity is 10 ns and the shortest pulse is 50 ns; the authors demonstrate operation at the maximum 133 MHz clock, achieving the advertised 7.5 ns resolution and 37.5 ns minimum pulse. The 264 kB SRAM eliminates the need for external memory for most experimental sequences, while the DMA‑driven PIO pipeline ensures deterministic timing even under heavy instruction loads.

Compared to FPGA solutions, the Pico‑based approach offers several clear advantages:

• Cost – A single Pico board costs a few dollars; dozens can be purchased for the price of one mid‑range FPGA.
• Power – The RP2040 consumes tens of milliwatts, orders of magnitude less than typical FPGA boards.
• Programming simplicity – Development can be done in C/C++ or MicroPython, avoiding HDL languages and proprietary toolchains.
• Scalability – Multiple boards can be networked via USB, each providing up to four independent outputs; the architecture naturally supports parallel expansion.

Limitations are also acknowledged: the timing ceiling is set by the 133 MHz system clock, so sub‑nanosecond resolution is unattainable; SRAM capacity caps the length of a single instruction sequence (≈30 k instructions); USB CDC bandwidth may become a bottleneck for ultra‑high‑rate re‑programming, suggesting future integration of faster interfaces (USB 3.0, Ethernet). Multi‑board synchronization relies on a shared external reference clock, requiring additional distribution hardware.

In conclusion, the authors demonstrate that a modern microcontroller equipped with dedicated I/O and DMA engines can replicate many of the timing capabilities traditionally reserved for FPGAs, while delivering substantial savings in cost, power, and development effort. The platform is especially well‑suited for experiments that need hundreds of synchronized digital triggers, such as large‑scale quantum‑information processors or complex AMO setups. Future work is proposed on high‑speed interface integration, refined clock distribution, and extending memory capacity to accommodate even longer pulse sequences.