Testability of Reversible Iterative Logic Arrays

📝 Abstract

Iterative Logic Arrays (ILAs) are ideal as VLSI sub-systems because of their regular structure and its close resemblance with FPGAs (Field Programmable Gate Arrays). Reversible circuits are of interest in the design of very low power circuits where energy loss implied by high frequency switching is not of much consideration. Reversibility is essential for Quantum Computing. This paper examines the testability of Reversible Iterative Logic Arrays (ILAs) composed of reversible k-CNOT gates. For certain ILAs it is possible to find a test set whose size remains constant irrespective of the size of the ILA, while for others it varies with array size. Former type of ILAs is known as Constant-Testable, i.e. C-Testable. It has been shown that Reversible Logic Arrays are C-Testable and size of test set is equal to number of entries in cells truth table implying that the reversible ILAs are also Optimal-Testable, i.e. O-Testable. Uniform-Testability, i.e. U-Testability has been defined and Reversible Heterogeneous ILAs have been characterized as U-Testable. The test generation problem has been shown to be related to certain properties of cycles in a set of graphs derived from cell truth table. By careful analysis of these cycles an efficient test generation technique that can be easily converted to an ATPG program has been presented for both 1-D and 2D ILAs. The same algorithms can be easily extended for n-Dimensional Reversible ILAs.

💡 Analysis

Iterative Logic Arrays (ILAs) are ideal as VLSI sub-systems because of their regular structure and its close resemblance with FPGAs (Field Programmable Gate Arrays). Reversible circuits are of interest in the design of very low power circuits where energy loss implied by high frequency switching is not of much consideration. Reversibility is essential for Quantum Computing. This paper examines the testability of Reversible Iterative Logic Arrays (ILAs) composed of reversible k-CNOT gates. For certain ILAs it is possible to find a test set whose size remains constant irrespective of the size of the ILA, while for others it varies with array size. Former type of ILAs is known as Constant-Testable, i.e. C-Testable. It has been shown that Reversible Logic Arrays are C-Testable and size of test set is equal to number of entries in cells truth table implying that the reversible ILAs are also Optimal-Testable, i.e. O-Testable. Uniform-Testability, i.e. U-Testability has been defined and Reversible Heterogeneous ILAs have been characterized as U-Testable. The test generation problem has been shown to be related to certain properties of cycles in a set of graphs derived from cell truth table. By careful analysis of these cycles an efficient test generation technique that can be easily converted to an ATPG program has been presented for both 1-D and 2D ILAs. The same algorithms can be easily extended for n-Dimensional Reversible ILAs.

📄 Content

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Testability of Reversible Iterative Logic Arrays

Avik Chakraborty

Abstract— Iterative Logic Arrays (ILAs) are ideal as VLSI sub- systems because of their regular structure and it’s close resemblance with FPGAs (Field Programmable Gate Arrays). Reversible circuits are of interest in the design of very low power circuits where energy loss implied by high frequency switching is not of much consideration. Reversibility is essential for Quantum Computing. This paper examines the testability of Reversible Iterative Logic Arrays (ILAs) composed of reversible k-CNOT gates. For certain ILAs it is possible to find a test set whose size remains constant irrespective of the size of the ILA, while for others it varies with array size. Former type of ILAs is known as Constant-Testable, i.e. C-Testable. It has been shown that Reversible Logic Arrays are C-Testable and size of test set is equal to number of entries in cell’s truth table implying that the reversible ILAs are also Optimal-Testable, i.e. O-Testable. Uniform-Testability, i.e. U-Testability has been defined and Reversible Heterogeneous ILAs have been characterized as U- Testable. The test generation problem has been shown to be related to certain properties of cycles in a set of graphs derived from cell truth table. By careful analysis of these cycles an efficient test generation technique that can be easily converted to an ATPG program has been presented for both 1-D and 2D ILAs. The same algorithms can be easily extended for n-Dimensional Reversible ILAs.

Index Terms—C-Testable, Iterative Logic Arrays, Bijective, U- Testable, Test Generation, ATPG

I. INTRODUCTION Reversible circuits are classical counterparts of Quantum Circuits which are inherently reversible. It has manifold applications in low power CMOS quantum computing, nanotechnology, optical computing, computer graphics, DNA technology and cryptography. In quantum circuits, the unit of quantum information is a qubit, which can be either in a zero state (|0>) or a one state (|1>). It can also be in a state which is a superposition of these states, i.e. α|0> + β|1> where α and β are complex numbers called amplitudes so that |α|2 + |β|2 = 1. Quantum computation can solve exponentially hard problems (ex. Prime Factorization) in polynomial time by exploiting the superposition.

Reversible circuits have the property that every distinct input pattern yields a distinct output pattern, and the input and output wires are equal in number. Such circuits are of interest for several reasons. Reversible circuits are information-loss less and hence tend to dissipate relatively little energy. According to Landauer’s principle [1, 2], it is possible to construct a computer using reversible circuits that can compute with arbitrarily small amounts of energy. Erasure of 1 bit information gives rise to entropy by kloge2 and heat dissipation by kT loge2 where T is the temperature of the environment. Here k is boltzmann’s constant. Reversibility is an essential property of the circuits needed for quantum computation [3], which is a major motivation behind this study.

The testing of ILAs has been widely studied in the past and even more so in recent times due to advances in VLSI which have made these structures attractive to the circuit designer. Most test generation techniques use the regular cell interconnection structure of the ILAs in one way or the other [4, 5, 6, 7, 8]. Stroud etal [9] have used concept of ILA testing for a BIST approach to FPGA testing.

In this paper we examine testability of Iterative Logic Arrays
(ILA’s) constructed from a library of reversible gates called k- controlled-NOT (k-CNOT) gates. A k-CNOT gate has k + 1 input wires and k + 1 output wires. It transmits the first k input signals unchanged, and inverts the last input signal iff the first k inputs are all 1; clearly this input-output mapping is bijective. Figure 1 shows examples of k-CNOTs and the standard graphic symbols used for them. If k = 0, a k-CNOT is a simple NOT gate or inverter. A 1-CNOT gate is simply known as CNOT gate. A 2-CNOT gate is known as Toffoli gate. (NOT, CNOT, TOFFOLI) constitute NCT library. Since a Toffoli gate can implement the NAND function, any Boolean function can be implemented by a k-CNOT circuit. A k-CNOT gate can be implemented using 1 k-input AND gate and an EXOR gate as shown in Fig 2. Frequency of switching in a k-CNOT gate is very less, i.e. 1/2k. . Figure 3 shows k-CNOT implementation of a single ILA cell which can be connected as 1- D homogeneous array of identical cells to construct a reversible Ripple Carry Adder (RCA).

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Figure 1: (a) NOT (b) CNOT and (c) general k-CNOT gate The paper is organized as follows. In section 2 the assumed Single Cell Fault (SCF) model has been discussed. In section 3, how 1-D array of identical cells can realize a reversibl

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