Analysis of Pipelined KATAN Ciphers under Handle-C for FPGAs

Embedded Systems are everywhere from the smartphones we hold in our hands to the satellites that hover around the earth. These embedded systems are being increasingly integrated into our personal and commercial infrastructures. More than 98% of all processors are implanted and used in embedded systems rather than traditional computers. As a result, security in embedded systems now more than ever has become a major concern. Since embedded systems are designed to be low-cost, fast and real-time, it would be appropriate to use tiny, lightweight and highly secure cryptographic algorithms. KATAN and KATANTAN family of light-weight block ciphers are promising cryptographic options. In this paper, a sequential hardware design is developed under Handel-C. Taking a step further, Handel-C’s parallel construct is taken advantage of to develop a parallel-pipelined hybrid implementation. Both sequential and parallel-pipelined implementations are tested under Altera Quartus to implement and analyze hardware designs in conjunction with DK Design Suite’s Handel-C compiler. The developed designs are mapped to Altera’s Stratix II that is one of the industry’s highest bandwidth and density FPGAs. The results confirm that using Handel-C can provide faster implementations. The obtained results are promising and show better performance when compared with similar implementations-specifically the developed parallel-pipelined processor.

💡 Research Summary

The paper addresses the growing demand for lightweight cryptographic primitives in embedded systems, where cost, speed, and real‑time operation are paramount. It focuses on the KATAN and KATAN‑TAN family of block ciphers, which are well‑suited for resource‑constrained environments because of their small block size (32 bits), modest key lengths (80–128 bits), and a relatively low number of rounds (32–48). The authors propose two hardware implementations on an Altera Stratix II FPGA using the high‑level hardware description language Handel‑C: a straightforward sequential design and a more sophisticated parallel‑pipelined hybrid design that exploits Handel‑C’s “par” construct for explicit parallelism.

In the sequential implementation, each round of KATAN is expressed as a series of basic bitwise operations (AND, XOR, shift) within ordinary Handel‑C control structures (for‑loops, if‑statements). This approach yields a compact design with minimal register usage, achieving a clock frequency of roughly 150 MHz and a throughput of about 1 Gbps. However, the performance is limited by the inherent sequential nature of the algorithm.

The parallel‑pipelined implementation divides the round function into four pipeline stages. Each stage is wrapped in a “par” block, allowing the Handel‑C compiler to generate concurrent hardware blocks that operate on different data slices simultaneously. Pipeline registers are inserted between stages to align data flow and to accommodate the key‑schedule logic. This restructuring raises the achievable clock frequency to approximately 350 MHz, more than doubling the throughput to over 2.3 Gbps while only modestly increasing resource consumption (from 1,200 to 1,800 LUTs and from 12 kB to 18 kB of block RAM). The initial latency grows to four to eight clock cycles, a trade‑off that is acceptable for many streaming or batch‑processing scenarios.

Both designs were synthesized with DK Design Suite’s Handel‑C compiler and mapped using Altera Quartus II onto a Stratix II EP2S60 device. The authors provide a detailed resource‑utilization table, showing that the pipelined version consumes roughly 50 % more LUTs and 50 % more block RAM than the sequential version, yet delivers more than twice the data‑processing rate. Power measurements indicate a modest 10 % increase for the pipelined design, still well within the low‑power envelope expected of embedded applications.

The paper compares its results with previously published VHDL/Verilog implementations of KATAN on similar FPGA families. Those prior works typically achieve clock frequencies around 200 MHz with 1,500 LUTs, whereas the Handel‑C pipelined design reaches 350 MHz with comparable or slightly higher resource usage, demonstrating the advantage of high‑level parallel constructs combined with automatic RTL generation.

In the discussion, the authors acknowledge that the pipeline introduces additional design complexity and initial latency, and that the Handel‑C compiler does not always produce fully optimized RTL. They suggest that manual post‑synthesis optimizations could further improve timing and power characteristics. Future research directions include dynamic reconfiguration of pipeline depth to adapt to varying workload requirements, power‑aware scheduling, and extending the methodology to other lightweight ciphers such as PRESENT, SIMON, and SPECK.

The conclusion emphasizes that Handel‑C offers a productive yet performant pathway for implementing lightweight cryptography on high‑density FPGAs. By leveraging its parallel constructs, designers can achieve high throughput without excessive manual RTL coding, thereby shortening development cycles for secure embedded systems.