A Mixed-Signal Structured AdEx Neuron for Accelerated Neuromorphic Cores

Here we describe a multi-compartment neuron circuit based on the Adaptive-Exponential I&F (AdEx) model, developed for the second-generation BrainScaleS hardware. Based on an existing modular Leaky Integrate-and-Fire (LIF) architecture designed in 65 nm CMOS, the circuit features exponential spike generation, neuronal adaptation, inter-compartmental connections as well as a conductance-based reset. The design reproduces a diverse set of firing patterns observed in cortical pyramidal neurons. Further, it enables the emulation of sodium and calcium spikes, as well as N-Methyl-D-Aspartate (NMDA) plateau potentials known from apical and thin dendrites. We characterize the AdEx circuit extensions and exemplify how the interplay between passive and non-linear active signal processing enhances the computational capabilities of single (but structured) on-chip neurons.

💡 Research Summary

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The paper presents a mixed‑signal, multi‑compartment neuron circuit that implements the Adaptive‑Exponential Integrate‑and‑Fire (AdEx) model in 65 nm CMOS for the second‑generation BrainScaleS neuromorphic platform. Building on a previously published modular Leaky‑Integrate‑and‑Fire (LIF) architecture, the authors augment the design with exponential spike generation, spike‑triggered adaptation, conductance‑based reset, and tunable inter‑compartmental conductances. The circuit is capable of reproducing a wide variety of firing patterns observed in cortical pyramidal neurons, including regular spiking, bursting, calcium spikes, and long‑lasting NMDA plateau potentials that are characteristic of apical and thin dendrites.

The AdEx model is realized with two state variables: the membrane voltage V_mem and an adaptation current w. Equation (1) of the model is mapped onto a membrane capacitor C_mem, a leak OTA that provides a conductance g_leak, and an exponential circuit that injects a current proportional to exp((V_mem‑V_T)/ΔT). The adaptation dynamics are split into a sub‑threshold conductance a, generated by a separate OTA (g_a), and a spike‑triggered charge pump that updates the adaptation voltage V_w stored on a high‑value tunable resistor‑capacitor pair (g_w, C_w). The resistor is implemented as a bulk‑drain connected PMOS pair, giving a programmable resistance range from 16 MΩ to 600 MΩ, which translates into a wide range of adaptation time constants τ_w = R_w·C_w.

A key innovation is the conductance‑based reset. During the refractory period the same OTA that implements the leak is switched to a high‑conductance mode (≈10 × g_leak), connecting the membrane node to a programmable reset potential V_rst while still allowing synaptic currents to flow. This enables the neuron to hold a depolarized plateau (e.g., NMDA potential) for a digitally programmable duration, up to one second in biological time (≈1 ms in hardware due to the 1000× acceleration).

Multi‑compartment functionality is achieved by interconnecting adjacent neuron cores with programmable conductances g_ic controlled by transmission‑gate switches S_ic. By merging membrane capacitors, the architecture can realize a larger effective membrane (high‑input‑count mode) or keep them separate to model distinct somatic and dendritic compartments. Each compartment can be configured independently to generate sodium spikes, calcium spikes, or NMDA plateaus, allowing the emulation of complex dendritic computations such as local non‑linear integration and back‑propagating action potentials.

The prototype chip contains an array of 32 neurons each coupled to a 32 × 32 synapse matrix. Synaptic events are delivered as 6‑bit DAC‑coded current pulses of 4 ns duration, with separate excitatory and inhibitory lines. All analog parameters (14 currents, 6 voltages) are stored in on‑chip analog memory with 10‑bit resolution, while 40 digital configuration bits per neuron are held in SRAM. The authors provide measured waveforms demonstrating: (i) standard LIF spiking, (ii) AdEx exponential spikes with adaptive after‑hyperpolarization, (iii) calcium‑like broad spikes, (iv) NMDA plateau potentials lasting up to the programmed duration, and (v) multi‑compartment interactions where a dendritic compartment drives somatic spiking.

In the discussion the authors compare their approach to other neuromorphic implementations, highlighting that the conductance‑based reset and high‑value tunable resistor are essential for realistic plateau dynamics, which are absent in fixed‑reset LIF designs. The mixed‑signal nature preserves the low‑power benefits of analog computation while the digital configurability enables rapid re‑programming of neuronal phenotypes. The circuit operates 1000× faster than biological time, allowing accelerated learning experiments. The work paves the way for integration into the larger HICANN‑DLS wafer‑scale chip, where many such structured neurons will support large‑scale, biologically plausible network simulations.